Papers by Dr. Sanjeet Kumar Sinha
E3S Web of Conferences, 2020
The signal processing is advancing day by day as its needs and in wireline/wireless communication... more The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.
2021 5th International Conference on Electronics, Communication and Aerospace Technology (ICECA)
The emerging technologies such as Internet of Things (IoT) and Biomedical electronics in the fiel... more The emerging technologies such as Internet of Things (IoT) and Biomedical electronics in the field of ultra-lower power applications have a major challenge of power scaling using modern CMOS technologies. The devices used in these technologies (such as biomedical and IoT based applications, require ultra-low power consumption as well as a scaled switching device. To achieve an energy efficient switching with lesser power consumption, a device with super steeper subthreshold swing is required. The superior switching characteristics of Tunnel Field Effect Transistor (TFET), facilitates the current conduction by Band to Band Tunnelling (BTBT) mechanism while maintaining adequate performance, makes it suitable for low power applications. Negative capacitance phenomenon, if applied to TFET, can further enhance the current ratio Ion/Ioff and makes subthreshold swing super steep. This work proposes a heterojunction Negative Capacitance Tunnel FET (NC-TFET) device that has achieved an average SS of 9.38 mv/dec in case of PZT material with transconductance gm of 2.516. The enhancement of device design and analysis of analog performance parameters of proposed NC-TFET covers the future scope of this work.
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Abstract—In this paper at first a brief review of carbon nanotubes (CNTs) is given and then an ex... more Abstract—In this paper at first a brief review of carbon nanotubes (CNTs) is given and then an extensive survey of CNTFET (carbon nanotube field effect transistor) based logic circuits are discussed with the most recently reported CNTFET logic circuits. Keywords— ...
Materials Today: Proceedings
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)
Wireless Personal Communications
Chapman and Hall/CRC eBooks, Jun 27, 2022
Engineering Research Express
In this work, the performance of negative capacitance field effect transistor is closely investig... more In this work, the performance of negative capacitance field effect transistor is closely investigated with different source material to improvise the transfer characteristics and sub-threshold swing. Tunnel Field Effect Transistor (TFET) being a strong competitor of conventional MOSFET for low power applications has its abilities to pull down Subthreshold Swing (SS) below fundamental limit but it has its own limitations of lower ION current and existence of ambipolar region for lower VGS voltage range. This ambipolar behavior is strongly seen in case of silicon source NCTFET but when source material is replaced with Germanium, a heterojunction is formed at source channel junction, and because of that, improvised result is obtained in terms of steeper subthreshold slope and ION/IOFF ratio. This work compares the transfer characteristics obtained in case of Si-Source and Ge-Source Negative Capacitance Tunnel Field Effect Transistor (NCTFET). The results obtained indicates that heteroj...
In case of images & videos, the encoding philosophy is substantially different as compared to tha... more In case of images & videos, the encoding philosophy is substantially different as compared to that of speech. The very basic difference between image & speech is that, the speech signals are one dimensional, whereas the images are two dimensional in nature. Modern day images can have the resolution in the range of ‘1024 x 1024’, this means there will 1 Mega Pixels & for color images, 1 pixel is represented by 24 bits (8 bits for each pixel component of red, green & blue), that means there are 24 Megabits in a single still image. In videos such still images are changing at 30 frames per second, so the basic bit rate going to be 30 times of 24 Megabits, this leads to the explosion in information. This demands compression of images at significant extent. In this work, image compression is achieved by using transformation based on modified lifting wavelet structure followed by quantization based on modified set partition in hierarchical tree (SPIHT) algorithm. This modification in SPIHT...
2022 IEEE VLSI Device Circuit and System (VLSI DCS)
Nanoscience & Nanotechnology-Asia
Background: In the nanometer regime, the impact of temperature is quite dominant in the device ch... more Background: In the nanometer regime, the impact of temperature is quite dominant in the device characteristics. Objectives: A comparative study of L-shaped Tunnel Field Effect Transistors (TFETs) and Ushaped TFETs with temperature variation. Methods: The effect of temperature has been studied for the device characteristics in terms of surface potential, electric field, and transfer characteristics using the Synopsys TCAD tool. Results: The ON current and OFF current of L-shaped and U-shaped TFETs structure shows the enhanced performance due to the large area of channel length. The addition of n-type pocket under the source enhances both devices ON current and OFF current. Both L-shaped and U-shaped TFETs structures are easy to fabricate and cost-effective due to the use of already established Si technology. Conclusion: In next-generation devices, the superior performance of L and U-shaped TFETs structure makes it a promising contender for low power applications as their subthreshold...
2022 International Conference on Electronics and Renewable Systems (ICEARS)
In this work, an accurate and computationally efficient analytical model for Negative Capacitance... more In this work, an accurate and computationally efficient analytical model for Negative Capacitance Tunnel Field Effect Transistor (NCTFET) is presented. The model discussed in this paper is based on capacitance matching and Landau-Khalatnikov equations implemented on conventional Tunnel Field Effect Transistor (TFET). The current-voltage model is developed by calculating the capacitance and voltage across ferroelectric layer. The ψs calculated is used subsequently to obtain the charge and capacitance behavior. The results shows that there is a good match between modelling results and obtained from Synopsys TCAD simulations. The calculations includes various device parameters such as charges, VFE, drain current, subthreshold slope (SS). The impact of Fe material thickness is also seen in ID-VG characteristics of proposed device. The parameters analyzed from the reported model shows perfect matching with Synopsys TCAD simulations making it suitable for circuit simulations.
Silicon, 2022
The aggressive scaling of metal-oxide-semiconductor (MOS) devices has transcended the micrometer ... more The aggressive scaling of metal-oxide-semiconductor (MOS) devices has transcended the micrometer scale into nanometer scale. However, scaling in the nanoscale regime faces numerous issues like threshold voltage roll-off, and short channel effects (SCEs). This paper presents a numerically simulated Ge-source based Tunnel Field Effect Transistor with (TFETs) SiO 2 segregation between the channel and drain. The developed device has been compared with conventional TFET and without isolated heterojunction TFET. The use of oxide segregation between channel and drain enhances the performance of the device in terms of ON-state current as well as subthreshold swing (SS). The electrical characteristics such as surface potential, electric field, transfer characteristics, output characteristics of the proposed device have been studied. The temperature variation of the proposed device has also been studied. The proposed device offers high ON current of 3 × 10 −4 A, I ON /I OFF ratio of ~10 11, a...
This paper presents a numerically simulated Ge-source based Tunnel Field Effect Transistor with (... more This paper presents a numerically simulated Ge-source based Tunnel Field Effect Transistor with (TFETs) SiO 2 segregation between the channel and drain. The developed device has been compared with conventional TFET and without isolated heterojunction TFET. The use of oxide segregation between channel and drain enhances the performance of the device in terms of ON-state current as well as subthreshold swing (SS). The electrical characteristics such as surface potential, electric field, transfer characteristics, output characteristics of the proposed device have been studied. The temperature variation of the proposed device has also been studied. The proposed device offers high ON current of 3x10 4 A, I ON /I OFF ratio of ~10 11, and enhanced SS of 30 mV/dec. The validity of the proposed device has been done by Synopsys Sentaurus TCAD.
2021 2nd International Conference for Emerging Technology (INCET), 2021
In this paper a extensive survey of FDSOI based FET Devices is done for low power application. FD... more In this paper a extensive survey of FDSOI based FET Devices is done for low power application. FD-SOI FET has lots of advantages because of the oxide thickness, Buried Oxide (BOX) layers which helps to prevent from leakage power problem, the structure of FDSOI FET help to boost the researchers to focus on Nano-scale devices. Nowadays people interested in portable and low power devices. Scaling in threshold voltage gives better low power results and the threshold voltage of FD-SOI is 0.3642V [35] which is low compare to conventional MOSFET. Subthreshold swing makes an important role in making low power devices for low power devices Subthreshold Swing must be low, In FDSOI the Subthreshold swing value range between 65-80 [49]. They need devices with low cost, low power, and lower thermal resistance. For these kinds of applications, FD-SOI technology is more efficient.
DRAM’s are essential for memory-based electronics devices and the usage of RAM is increasing day ... more DRAM’s are essential for memory-based electronics devices and the usage of RAM is increasing day by day to reach the user's expectation the products are get designed based on low power and portable. Power dissipation is a major issue to solve this issue researchers are focusing on low power circuits and trying to design the circuits with less number of the transistor so that it will consume less amount of power. In this paper, three structures are presently based on MOSFET technology and CNTFET technology. MOSFET model structures are divided into two they are 1.DRAM circuit with Tri-state buffers and 2. DRAM circuit without Tri-state buffers. CNTFET based structure is built with the help of ‘CarbonNanoTube-FET’s and the structure is the same as DRAM without Tri-state buffers. Power analysis, voltage, delay are evaluated with the help of cadence virtuoso and LTspice Tools.
Due to the continuous scaling of the conventional metal oxide semiconductor field effect transist... more Due to the continuous scaling of the conventional metal oxide semiconductor field effect transistor (MOSFET), we have finally reached to a limit where industry is not able to sustain the scaling of MOSFET due to its ultra nano scale range (below 50 nm). The reason attributed are the leakage currents, higher power dissipation, threshold roll-off, etc. Thus, other alternatives need to be studied in order to sustain the scalability. In that regard, this paper focuses on carbon nano tube field effect transistors (CNTFET) as one of the solutions to the existing problems. We have explained the device details, operation and the characteristics of CNTs.
This paper presents a simulation study of channel material Al0.2Ga0.8As in tunnel field effect tr... more This paper presents a simulation study of channel material Al0.2Ga0.8As in tunnel field effect transistor. An extensive simulation is used to analyses ac and dc analysis of the proposed device. It is observed that the proposed device shows high on/off ratio ~10 and the subthreshod swing of~30 mV/dec when Al0.2Ga0.8As is used as channel material in tunnel field effect transistor. This study shows better performance in dc and ac analysis with compare to other existing channel materials.
2021 International Conference on Computer Communication and Informatics (ICCCI), 2021
Network on Chip (NoC) is an emerging design platform for on chip connections which overcomes issu... more Network on Chip (NoC) is an emerging design platform for on chip connections which overcomes issues faced by conventional bus build communication. The main aim in design of any NoC is to reduce average latency and deflection rate without reducing the operating speed. To overcome the surge in design area as well as Static and Dynamic power consumption issues in case on normal VC (Virtual Channel) based router, deflection routing concept has been suggested. The routing process used in case of BLESS (Buffer Less Router) depends upon deflection of packets to an unintended port. To curtail excess power consumption and design area, researchers have come up with buffer less and littlest buffer router. In this paper Tiled Chip Multiple Processor (TCMP) and CHIPPER router parameter details are discussed. Permutation deflection logic is used in this paper. Results shows that as compared to normal VC Buffer router, CHIPPER Router reduces Normalized Router area by 36.2% compared to BLESS Router...
Due to rapid scaling of semiconductor devices, threshold voltage is also scaled down to some exte... more Due to rapid scaling of semiconductor devices, threshold voltage is also scaled down to some extend which further increases the leakage current of devices. In this paper, Impact of chiral vector on threshold voltage of carbon nanotube is observed for CNTFET device. We have simulated the CNTFET with a number of different combinations of chiral vector pairs using HSPICE tool and considered the Stanford model of CNTFET devices for simulation. It is much clear from the simulated result that in order to have high threshold voltages in CNTFET which is emerging device in nanometer regime, the chiral vectors (m,n) will be relatively smaller.
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Papers by Dr. Sanjeet Kumar Sinha