The scope of most high-level synthesis efforts to date has been at the level of a single behavior... more The scope of most high-level synthesis efforts to date has been at the level of a single behavioral model represented as a control/data-flow graph. The communication between concurrently executing processes and its requirements in terms of timing and resources have largely been neglected. This restriction limits the applicability of most existing approaches for complex system designs. This paper describes a methodology for the synthesis of interfaces in concurrent systems under detailed timing constraints. We model inter-process communication using blocking and nonblocking messages. We show how the relationship between messages over time can be abstracted as a constraint graph that can be extracted and used during synthesis. We describe a novel technique called interface matching that minimizes the interface cost by scheduling each process with respect to timing information of other processes communicating with it. By scheduling the completion of operations, some blocking communicat...
High-level synthesis is the transformation from a behavioral level specification of hardware, thr... more High-level synthesis is the transformation from a behavioral level specification of hardware, through a series of optimizations and translations, to an implementation in terms of logic gates and registers. The success of a high-level synthesis system is heavily dependent on how effectively the high-level language captures the ideas of the designer in a simple and understandable way. Furthermore, as system-level issues such as communication protocols and design partitioning dominate the design process, the ability to specify constraints on the timing requirements and resource utilization of a design is necessary to ensure that the design can integrate with the rest of the system. In this paper, a hardware description language called HardwareC is presented. HardwareC supports both declarative and procedural semantics, it has a C-like syntax, and it is extended with notion of concurrent processes, message passing, timing constraints via tagging, resource constraints, explicit instantiation of models, and template models. The language is used as the input to the HercuZeslHebe High-level Synthesis System.
This invention is directed to a window shade cutter for manually trimming the end of a rolled sha... more This invention is directed to a window shade cutter for manually trimming the end of a rolled shade to conform to the size of the window opening into which the shade is to be mounted. The cutter includes a cylindrical clamping sleeve, having an annular guide groove at one end thereof, adapted to slip over the shade and clamp in place and a cutoff tool receivable in the guide groove including a generally planar U-shaped holder and a planar blade mounted on the holder. In a preferred form, the blade has a rounded, dull end with a central V-shaped notch therein in which a pair of cutting edges are located. The cutoff tool is adapted to interlock in the guide groove and to rotate about the shade with cutting of the shade taking place in the V-shaped notch a few layers at a time as the tool is urged towards the shade and rotated. In accordance with the invention disclosed, window shades can be safely and easily trimmed by the consumer in the home thus eliminating the need for cutting machines.
... contrast to micro-architectural synthesis systems that use a pre-defined set of library eleme... more ... contrast to micro-architectural synthesis systems that use a pre-defined set of library elements as building blocks, Hercules and Hebe treat each ... can be synthesized in a variety of different implementation styles, the designer is often constrained to elements of a particular li-brary ...
Abstract Hardware resources can be shared to reduce the area of the resulting design. The synthes... more Abstract Hardware resources can be shared to reduce the area of the resulting design. The synthesis system must ensure that no resource conflicts arise due to simultaneous access of a shared hardware,resource. With traditional scheduling formulations where operations are statically assigned to control steps, conflict resolution simply determines whether two operations can execute concurrently based on their control step assignment. In this case, operations are assumed,to have fixed execution delay. For hardware,models,that supports external synchronization and handshaking, however, operations may have unbounded execution delay , e.g., detecting the rising edge of a signal. The presence of unbounded,delay operations invalidates the traditional scheduling and conflict resolution approaches. We formulate in this paper conflict resolution as the task of serializing operations bound,to the same,hardware resource. A technique called constrained conflict resolution is presented to resolve resource conflicts such that the resulting design satisfies the required timing and handshaking,requirements. The timing constraint topology is used to reduce the computation,time of the algorithm. This technique extends the relative scheduling formulation to support resource sharing under timing constraints. We describe both exact and heuristic algorithms to resolve resource conflicts; these algorithms are implemented,in a synthesis system,called Hebe that is targeted towards the synthesis of Application-Specific Integrated Circuit designs. Results of applying the system to the design of benchmark,and complex,ASIC designs are presented. Keywords: Resource conflict resolution, high-level synthesis, automated synthesis, behavioral synthesis, hard-
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
Scheduling techniques are used in high-level synthesis of integrated circuits. Traditional schedu... more Scheduling techniques are used in high-level synthesis of integrated circuits. Traditional scheduling techniques assume fixed execution delays for the operations. For the synthesis of ASIC designs that interface with external signals and events, timing constraints and operations with unbounded delays, i.e. delays unknown at compile time, must also be considered. We present a relative scheduling formulation that supports operations with fixed and unbounded delays. In this formulation, the start time of an operation is specified in terms of offsets from the set of unbounded delay operations called anchors. We analyze first a novel property called well-posedness of timing constraints that is used to identify consistency of constraints in the presence of unbounded delay operations. We present an algorithm that will transform an ill-posed constraint graph into a minimally serialized well-posed constraint graph, if one exists. The anchors are then checked for redundancy, and we identify the minimum set of anchors that are required in computing the start time. We present an algorithm that schedules the operations relative to the anchors, which yields a minimum schedule that satisfies the timing constraints, or detects if no schedule exists, in polynomial time. Finally, we describe the generation of control logic from the resulting relative schedule. Analysis of the optimality and complexity of the algorithm is presented.
International Conference on Computer Aided Design, 1996
As the primary Department of Commerce bureau to assist with post-natural disaster economic recove... more As the primary Department of Commerce bureau to assist with post-natural disaster economic recovery, EDA received two distinct disaster supplemental appropriations totaling $500 million in Fiscal Year 2008. The appropriations are to be used for disaster relief, long-term recovery and restoration of infrastructure in areas covered by a declaration of major disaster under the Robert T. Stafford Disaster Relief and Emergency Assistance Act.
... The functionality is described in a C-based language extended for hardware description called... more ... The functionality is described in a C-based language extended for hardware description called ... Many synthesis systems and hardware description languages support only a specific design style, either ... We believe a more efective approach to design is to use a flexible underlying ...
Abstract Most approaches to control-unit optimization use a finite state machine model, where ope... more Abstract Most approaches to control-unit optimization use a finite state machine model, where operations are bound to control states. However, when synthesizing circuits from a higher, more abstract level of hardware specification that supports concurrency and ...
The scope of most high-level synthesis efforts to date has been at the level of a single behavior... more The scope of most high-level synthesis efforts to date has been at the level of a single behavioral model represented as a control/data-flow graph. The communication between concurrently executing processes and its requirements in terms of timing and resources have largely been neglected. This restriction limits the applicability of most existing approaches for complex system designs. This paper describes a methodology for the synthesis of interfaces in concurrent systems under detailed timing constraints. We model inter-process communication using blocking and nonblocking messages. We show how the relationship between messages over time can be abstracted as a constraint graph that can be extracted and used during synthesis. We describe a novel technique called interface matching that minimizes the interface cost by scheduling each process with respect to timing information of other processes communicating with it. By scheduling the completion of operations, some blocking communicat...
High-level synthesis is the transformation from a behavioral level specification of hardware, thr... more High-level synthesis is the transformation from a behavioral level specification of hardware, through a series of optimizations and translations, to an implementation in terms of logic gates and registers. The success of a high-level synthesis system is heavily dependent on how effectively the high-level language captures the ideas of the designer in a simple and understandable way. Furthermore, as system-level issues such as communication protocols and design partitioning dominate the design process, the ability to specify constraints on the timing requirements and resource utilization of a design is necessary to ensure that the design can integrate with the rest of the system. In this paper, a hardware description language called HardwareC is presented. HardwareC supports both declarative and procedural semantics, it has a C-like syntax, and it is extended with notion of concurrent processes, message passing, timing constraints via tagging, resource constraints, explicit instantiation of models, and template models. The language is used as the input to the HercuZeslHebe High-level Synthesis System.
This invention is directed to a window shade cutter for manually trimming the end of a rolled sha... more This invention is directed to a window shade cutter for manually trimming the end of a rolled shade to conform to the size of the window opening into which the shade is to be mounted. The cutter includes a cylindrical clamping sleeve, having an annular guide groove at one end thereof, adapted to slip over the shade and clamp in place and a cutoff tool receivable in the guide groove including a generally planar U-shaped holder and a planar blade mounted on the holder. In a preferred form, the blade has a rounded, dull end with a central V-shaped notch therein in which a pair of cutting edges are located. The cutoff tool is adapted to interlock in the guide groove and to rotate about the shade with cutting of the shade taking place in the V-shaped notch a few layers at a time as the tool is urged towards the shade and rotated. In accordance with the invention disclosed, window shades can be safely and easily trimmed by the consumer in the home thus eliminating the need for cutting machines.
... contrast to micro-architectural synthesis systems that use a pre-defined set of library eleme... more ... contrast to micro-architectural synthesis systems that use a pre-defined set of library elements as building blocks, Hercules and Hebe treat each ... can be synthesized in a variety of different implementation styles, the designer is often constrained to elements of a particular li-brary ...
Abstract Hardware resources can be shared to reduce the area of the resulting design. The synthes... more Abstract Hardware resources can be shared to reduce the area of the resulting design. The synthesis system must ensure that no resource conflicts arise due to simultaneous access of a shared hardware,resource. With traditional scheduling formulations where operations are statically assigned to control steps, conflict resolution simply determines whether two operations can execute concurrently based on their control step assignment. In this case, operations are assumed,to have fixed execution delay. For hardware,models,that supports external synchronization and handshaking, however, operations may have unbounded execution delay , e.g., detecting the rising edge of a signal. The presence of unbounded,delay operations invalidates the traditional scheduling and conflict resolution approaches. We formulate in this paper conflict resolution as the task of serializing operations bound,to the same,hardware resource. A technique called constrained conflict resolution is presented to resolve resource conflicts such that the resulting design satisfies the required timing and handshaking,requirements. The timing constraint topology is used to reduce the computation,time of the algorithm. This technique extends the relative scheduling formulation to support resource sharing under timing constraints. We describe both exact and heuristic algorithms to resolve resource conflicts; these algorithms are implemented,in a synthesis system,called Hebe that is targeted towards the synthesis of Application-Specific Integrated Circuit designs. Results of applying the system to the design of benchmark,and complex,ASIC designs are presented. Keywords: Resource conflict resolution, high-level synthesis, automated synthesis, behavioral synthesis, hard-
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
Scheduling techniques are used in high-level synthesis of integrated circuits. Traditional schedu... more Scheduling techniques are used in high-level synthesis of integrated circuits. Traditional scheduling techniques assume fixed execution delays for the operations. For the synthesis of ASIC designs that interface with external signals and events, timing constraints and operations with unbounded delays, i.e. delays unknown at compile time, must also be considered. We present a relative scheduling formulation that supports operations with fixed and unbounded delays. In this formulation, the start time of an operation is specified in terms of offsets from the set of unbounded delay operations called anchors. We analyze first a novel property called well-posedness of timing constraints that is used to identify consistency of constraints in the presence of unbounded delay operations. We present an algorithm that will transform an ill-posed constraint graph into a minimally serialized well-posed constraint graph, if one exists. The anchors are then checked for redundancy, and we identify the minimum set of anchors that are required in computing the start time. We present an algorithm that schedules the operations relative to the anchors, which yields a minimum schedule that satisfies the timing constraints, or detects if no schedule exists, in polynomial time. Finally, we describe the generation of control logic from the resulting relative schedule. Analysis of the optimality and complexity of the algorithm is presented.
International Conference on Computer Aided Design, 1996
As the primary Department of Commerce bureau to assist with post-natural disaster economic recove... more As the primary Department of Commerce bureau to assist with post-natural disaster economic recovery, EDA received two distinct disaster supplemental appropriations totaling $500 million in Fiscal Year 2008. The appropriations are to be used for disaster relief, long-term recovery and restoration of infrastructure in areas covered by a declaration of major disaster under the Robert T. Stafford Disaster Relief and Emergency Assistance Act.
... The functionality is described in a C-based language extended for hardware description called... more ... The functionality is described in a C-based language extended for hardware description called ... Many synthesis systems and hardware description languages support only a specific design style, either ... We believe a more efective approach to design is to use a flexible underlying ...
Abstract Most approaches to control-unit optimization use a finite state machine model, where ope... more Abstract Most approaches to control-unit optimization use a finite state machine model, where operations are bound to control states. However, when synthesizing circuits from a higher, more abstract level of hardware specification that supports concurrency and ...
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Papers by David Ku