2006 IEEE International Conference on Field Programmable Technology, 2006
Abstract A confident use of deep submicron VLSI systems requires the study of their behaviour in... more Abstract A confident use of deep submicron VLSI systems requires the study of their behaviour in the presence of faults. Field-Programmable Gate Arrays (FPGAs) are being used to conduct this study by means of fault injection in a very fast way. However, FPGA-based fault ...
Nowadays, cache memories are applicable to real-time systems with the help of tools that obtain t... more Nowadays, cache memories are applicable to real-time systems with the help of tools that obtain the worst-case execution time (WCET) of cached programs. However, these tools do not allow preemption, because from the point of view of program analysis, the number of preemptions is unknown. To face this problem, the cache-related preemption cost can be considered in the schedulability analysis, or annulled by the use of private cache partitions. This paper comprises a number of techniques using the ®rst or both solutions. This paper also explores the harmonic relationships among tasks to improve the estimation of the cache interference in the analysis.
This paper presents the prototype of an automatic and model-independent fault injection tool, to ... more This paper presents the prototype of an automatic and model-independent fault injection tool, to be used on an IBM-PC (or compatible) platform. The tool has been built around a commercial VHDL simulator and it is thought to implement different fault injection techniques. With this tool, a wide range of transient and permanent faults can be injected into medium-complexity models. Another remarkable aspect of the tool is the fact that it can analyse the results obtained from injection campaigns, in order to study the Error Syndrome of the system model and/or validate its faulttolerance mechanisms. Some results of various fault injection campaigns carried out to validate the Dependability of a fault-tolerant microcomputer system are shown. We have analysed the pathology of the propagated errors, measured their latencies, and calculated both error detection and recovery latencies and coverages.
Many,designers bet on reducing ,time-to-market costs by integrating ,off-the-shelf (OTS) cores ,i... more Many,designers bet on reducing ,time-to-market costs by integrating ,off-the-shelf (OTS) cores ,in embedded systems. However, only those cores exhibiting adequate dependability levels are suitable candidates for system integration. Hence, the development,of benchmarking ,techniques supporting the evaluation and comparison,of hardware OTS cores according,to different dependability estimators is a must. Although remarkable ,advances ,have ,been accomplished,during last years on the ,dependability benchmarking of software cores, little effort has been devoted so far to hardware,ones. This paper proposes amethodology,that sets the basis for comparing ,and ranking hardware ,off-the-shelf cores. It makes use of Field Programmable ,Gate Arrays capabilities for prototyping and emulating the cores behaviour under different execution profiles (workloads and faultloads). Different architectures of a ,processing ,core ,are considered as case ,study. Results obtained show the feasibility of this...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008
Deep submicron devices are expected to be increasingly sensitive to physical faults. For this rea... more Deep submicron devices are expected to be increasingly sensitive to physical faults. For this reason, faulttolerance mechanisms are more and more required in VLSI circuits. So, validating their dependability is a prior concern in the design process. Fault injection techniques based on the use of hardware description languages offer important advantages with regard to other techniques. Firstly, as this type of techniques can be applied during the design phase of the system, they permit reducing the time-to-market. Secondly, they present high controllability and reachability. Among the different techniques, those based on the use of saboteurs and mutants are especially attractive due to their high fault modeling capability. However, implementing automatically these techniques in a fault injection tool is difficult. Especially complex are the insertion of saboteurs and the generation of mutants. In this paper we present new proposals to implement saboteurs and mutants for models in VHDL which are easy-to-automate, and whose philosophy can be generalized to other hardware description languages.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008
Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence ... more Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently proposed as a means for speeding-up the fault injection process in VLSI systems models (fault emulation) and for reducing the cost of fixing any error due to their applicability in the first steps of the development cycle. However, only a reduced set of fault models, mainly stuck-at and bit-flip, have been considered in fault emulation approaches. This paper describes the procedures to inject a wide set of faults representative of deep-submicrometer technology, like stuck-at, bit-flip, pulse, indetermination, stuck-open, delay, short, open-line, and bridging, using the best suitable FPGAbased technique. This paper also sets some basic guidelines for comparing VLSI systems in terms of their availability and safety, which is mandatory in mission and safety critical application contexts. This represents a step forward in the dependability benchmarking of VLSI systems and towards the definition of a framework for their evaluation and comparison in terms of performance, power consumption, and dependability. Index Terms-Fault injection, field-programmable gate arrays (FPGAs), run-time reconfiguration, validation of VLSI circuits.
2006 International Conference on Field Programmable Logic and Applications, 2006
ABSTRACT A confident use of deep-submicron VLSI systems requires the study of their behaviour in ... more ABSTRACT A confident use of deep-submicron VLSI systems requires the study of their behaviour in the presence of faults, which has been traditionally conducted via model-based fault injection techniques. Although field-programmable gate arrays (FPGAs) allows for a fast execution ...
2006 IEEE International Conference on Field Programmable Technology, 2006
Abstract A confident use of deep submicron VLSI systems requires the study of their behaviour in... more Abstract A confident use of deep submicron VLSI systems requires the study of their behaviour in the presence of faults. Field-Programmable Gate Arrays (FPGAs) are being used to conduct this study by means of fault injection in a very fast way. However, FPGA-based fault ...
Nowadays, cache memories are applicable to real-time systems with the help of tools that obtain t... more Nowadays, cache memories are applicable to real-time systems with the help of tools that obtain the worst-case execution time (WCET) of cached programs. However, these tools do not allow preemption, because from the point of view of program analysis, the number of preemptions is unknown. To face this problem, the cache-related preemption cost can be considered in the schedulability analysis, or annulled by the use of private cache partitions. This paper comprises a number of techniques using the ®rst or both solutions. This paper also explores the harmonic relationships among tasks to improve the estimation of the cache interference in the analysis.
This paper presents the prototype of an automatic and model-independent fault injection tool, to ... more This paper presents the prototype of an automatic and model-independent fault injection tool, to be used on an IBM-PC (or compatible) platform. The tool has been built around a commercial VHDL simulator and it is thought to implement different fault injection techniques. With this tool, a wide range of transient and permanent faults can be injected into medium-complexity models. Another remarkable aspect of the tool is the fact that it can analyse the results obtained from injection campaigns, in order to study the Error Syndrome of the system model and/or validate its faulttolerance mechanisms. Some results of various fault injection campaigns carried out to validate the Dependability of a fault-tolerant microcomputer system are shown. We have analysed the pathology of the propagated errors, measured their latencies, and calculated both error detection and recovery latencies and coverages.
Many,designers bet on reducing ,time-to-market costs by integrating ,off-the-shelf (OTS) cores ,i... more Many,designers bet on reducing ,time-to-market costs by integrating ,off-the-shelf (OTS) cores ,in embedded systems. However, only those cores exhibiting adequate dependability levels are suitable candidates for system integration. Hence, the development,of benchmarking ,techniques supporting the evaluation and comparison,of hardware OTS cores according,to different dependability estimators is a must. Although remarkable ,advances ,have ,been accomplished,during last years on the ,dependability benchmarking of software cores, little effort has been devoted so far to hardware,ones. This paper proposes amethodology,that sets the basis for comparing ,and ranking hardware ,off-the-shelf cores. It makes use of Field Programmable ,Gate Arrays capabilities for prototyping and emulating the cores behaviour under different execution profiles (workloads and faultloads). Different architectures of a ,processing ,core ,are considered as case ,study. Results obtained show the feasibility of this...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008
Deep submicron devices are expected to be increasingly sensitive to physical faults. For this rea... more Deep submicron devices are expected to be increasingly sensitive to physical faults. For this reason, faulttolerance mechanisms are more and more required in VLSI circuits. So, validating their dependability is a prior concern in the design process. Fault injection techniques based on the use of hardware description languages offer important advantages with regard to other techniques. Firstly, as this type of techniques can be applied during the design phase of the system, they permit reducing the time-to-market. Secondly, they present high controllability and reachability. Among the different techniques, those based on the use of saboteurs and mutants are especially attractive due to their high fault modeling capability. However, implementing automatically these techniques in a fault injection tool is difficult. Especially complex are the insertion of saboteurs and the generation of mutants. In this paper we present new proposals to implement saboteurs and mutants for models in VHDL which are easy-to-automate, and whose philosophy can be generalized to other hardware description languages.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008
Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence ... more Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently proposed as a means for speeding-up the fault injection process in VLSI systems models (fault emulation) and for reducing the cost of fixing any error due to their applicability in the first steps of the development cycle. However, only a reduced set of fault models, mainly stuck-at and bit-flip, have been considered in fault emulation approaches. This paper describes the procedures to inject a wide set of faults representative of deep-submicrometer technology, like stuck-at, bit-flip, pulse, indetermination, stuck-open, delay, short, open-line, and bridging, using the best suitable FPGAbased technique. This paper also sets some basic guidelines for comparing VLSI systems in terms of their availability and safety, which is mandatory in mission and safety critical application contexts. This represents a step forward in the dependability benchmarking of VLSI systems and towards the definition of a framework for their evaluation and comparison in terms of performance, power consumption, and dependability. Index Terms-Fault injection, field-programmable gate arrays (FPGAs), run-time reconfiguration, validation of VLSI circuits.
2006 International Conference on Field Programmable Logic and Applications, 2006
ABSTRACT A confident use of deep-submicron VLSI systems requires the study of their behaviour in ... more ABSTRACT A confident use of deep-submicron VLSI systems requires the study of their behaviour in the presence of faults, which has been traditionally conducted via model-based fault injection techniques. Although field-programmable gate arrays (FPGAs) allows for a fast execution ...
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Papers by Daniel Gil