Papers by Sanatan Chattopadhyay
2018 International Symposium on Devices, Circuits and Systems (ISDCS)
In this work, a Ge Fin channel Field Effect Transistor (FinFET) with Silicon-Germanium (SiGe) emb... more In this work, a Ge Fin channel Field Effect Transistor (FinFET) with Silicon-Germanium (SiGe) embedded source/drain region has been studied using Sentaurus Technology Computer Aided Design (TCAD) process and device simulator from Synopsys and the impact of SiGe stressor material induced channel stress on the device performance has been investigated thoroughly. It is found that the SiGe embedded source/drain regions induce tensile stress in the channel that helps to improve the n-channel device performance. The amount of induced channel stress has been found to depend on the relative dimensions of the gate, source/drain, and Fin channel regions. A significant improvement of channel stress and hence the device performance, in terms of drive current (Ion) and Ion/Ioff ratio, is observed for higher source/drain volume and thinner Fin width device structure due to the enhancement of electron mobility by the induced stress, indicating better performance of the transistor. Also, more than 3× drive current improvement compared to unstrained device has been achieved for 25% Ge content in the SiGe stressor material.
Materials Chemistry and Physics
Department of Chemical Engineering, Calcutta Institute of Technology, West Bengal University of T... more Department of Chemical Engineering, Calcutta Institute of Technology, West Bengal University of Technology, Uluberia, Howrah-711 316, West Bengal, India Department of Chemistry, West Bengal State University, Barasat, Kolkata-700 126, India E-mail : [email protected] Department of Polymer Science and Technology, University of Calcutta, 92, Acharya Prafulla Chandra Road, Kolkata-700 009, India E-mail : [email protected] Department of Chemical and Biological Engineering, Industrial Membrane Research Institute, University of Ottawa, 161 Louis Pasteur St., Ottawa, ON, KIN 6N5, Canada Department of Electronic Science, University of Calcutta, 92, Acharya Prafulla Chandra Road, Kolkata-700 009, India Manuscript received 28 March 2017, accepted 13 April 2017 Recycling of waste is a major thrust area for decreasing environmental pollution. Disposed cigarette butts, a common waste material in our livelihood consisting of the cigarette filters, are toxic to aquatic life and d...
2018 IEEE Electron Devices Kolkata Conference (EDKCON), 2018
The effect of Silicon-Germanium (SiGe) volume in an embedded source and drain Si-FinFET device st... more The effect of Silicon-Germanium (SiGe) volume in an embedded source and drain Si-FinFET device structure has been studied in this article. The study has been carried out thoroughly using the process and device technology computer-aided design (TCAD) simulator from Synopsys. A new technique for incorporating uniaxial tensile stress in the Silicon channel region has been introduced by fractionally SiGe embedded source/drain region in 3-dimensional FinFET architecture. It has been found that when the SiGe length in source/drain regions become equal to the length of gate region from channel-source/drain interface induce maximum tensile stress of 274 MPa in the silicon channel which improves the performance of n-type Field Effect Transistor (FET) devices. However, fully SiGe embedded source/drain region induce conventional compressive channel stress of 513 MPa which helps to increase different performance parameters of p-channel devices. Thus, for the first time, it has been reported that by controlling the stressor length/volume, both tensile and compressive strain can be introduced in the channel of a Si-FinFET device structure. The channel, source/drain, and stressor regions have been observed to control the overall nature and amount of incorporated stress and thus the proposed design is capable of improving the performance of both p-type and n-type FinFETs without any fabrication overhead.
2017 IEEE Calcutta Conference (CALCON), 2017
The present work focuses on the influence of graphene nano-particles on the optical, electrical a... more The present work focuses on the influence of graphene nano-particles on the optical, electrical and photo-catalytic activity of p-CuO/n-Si heterojunction. Both the CuO and graphene nano-particle incorporated CuO (G-CuO) films are grown by Chemical Bath Deposition (CBD) method. A comparative study has been performed on the systematic change of the film morphology and optoelectronic property of the grown films. The study suggests that the electronic and photo-detecting properties of the CBD grown CuO films can be improved by incorporating graphene in it.
Brazilian Journal of Analytical Chemistry, 2019
Schematic representation of the system under investigation and variation of its electrical and op... more Schematic representation of the system under investigation and variation of its electrical and optical properties with varying concentration of naphthalene. Polyaromatic hydrocarbons (PAH) are organic compounds with fused benzene rings that have toxic and mutagenic properties, and have been well documented for their detrimental effect on animal and plant health. Naphthalene, a two-ring PAH, is a common water pollutant which has been linked to the disruption of immune system as well as deformation of red blood corpuscles in human and thereby raising substantial concerns. The present study quantitatively estimates naphthalene in its aqueous solution by employing electrical impedance spectroscopy (EIS), which is simultaneously supported by UV-vis spectral analysis. Naphthalene solutions of varying concentrations (0.2-1 ppm) are prepared and subjected to EIS as well as UV-visible spectroscopy. For the EIS based studies, the data is recorded for the frequency range of 1 KHz-1 MHz and electrical parameters such as capacitance, conductance and admittance are observed to increase from 3.5 pF-7.2 pF, 2.3 µS-6.1 µS and 2.4 µS-27.3 µS, Optical Analysis Authenticated Electrical Impedance Based Quantification of Aqueous Naphthalene Article 31 respectively, with varying naphthalene concentration in its solution. On the other hand impedance values are observed to decrease with the same. Naphthalene is itself a non-polar molecule and the formation of instantaneous dipoles originating from the interaction of such molecules governs the overall dielectric nature of the solution. UV-vis spectroscopic measurements of the solutions reveal the characteristic absorbance maxima at 216 nm for all the concentrations under investigation. Absorbance values are observed to increase with the relative strength of naphthalene in the solution and such values vary in the range of 0.02-0.16 au for the peak obtained. Thus by corroborating the electrical and the optical parameters, this study establishes a quick and handy method for detection of naphthalene in aqueous solutions and ascertains a framework for further work that can be done to formulate a naphthalene sensing device.
Physica E: Low-dimensional Systems and Nanostructures, 2017
In the current work, an analytical model for the design of vertically aligned silicon (Si) nanowi... more In the current work, an analytical model for the design of vertically aligned silicon (Si) nanowire metal-oxide-semiconductor (MOS) capacitor based multi-color photodetectors has been developed for the detection of entire visible spectrum with high spectral resolution. The photogeneration phenomena within the nanostructures are analyzed in detail by developing a quantum field model associated with second quantization electron-photon field operators. The non-equilibrium Green's function (NEGF) formalism is employed to solve the relevant equations. The study shows that the proposed device with specified design of diametervoltage combinations is capable of detecting 64 spectral bands of the entire visible spectrum (380 nm to700 nm) directly with a very high resolution of 5 nm wavelength. Such direct sensing of each wavelength is observed to be independent of the fluctuations of illumination intensity. The device is designed to obtain a full-width-at-half-maximum (FWHM) smaller than the spectral resolution (5 nm) for each wavelength of the visible range, which indicates a very high quality digital imaging/sensing method. Such devices may be a potential alternative for the future nanoelectronics based photodevices for superior sensing/imaging applications.
Journal of Applied Physics, 2016
In this article, we propose a novel optoelectronic band-to-band tunnel field effect transistor wi... more In this article, we propose a novel optoelectronic band-to-band tunnel field effect transistor with a Si photo-gate, for multi-spectral sensing of near-infrared light in the wavelength range of 0.7 μm–1 μm. Based on the line tunneling approach, a drain current model has been developed to illustrate the device operating principle. The model incorporates the effect of photo-generation in the photo-gate in terms of the resulting photo-voltage. Good agreement with device simulation results indicates overall correctness of the developed model. The spectral response of the device has been studied in terms of its input and output characteristics, and the spectral sensitivity has been defined in terms of the change in current, in response to the change in the illumination wavelength. The proposed device can resolute closely spaced spectral lines (∼100 nm) in the wavelength range of 0.7 μm–1 μm, due to the combined effects of steep average sub-threshold swing of ∼19 mV/dec, over five current...
Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, 2003
Single and dual n-channel strained Si MOSFETs, fabricated by the same high thermal budget process... more Single and dual n-channel strained Si MOSFETs, fabricated by the same high thermal budget process, are compared for the first time. Si 1-x Ge x virtual substrates, having 0.1 < x < 0.3, are used to compare off-state and on-state device performance. Transconductances and current drive up to 240% higher than control Si MOSFETs are demonstrated. Electron mobility is found to peak using a virtual substrate composition of Si 0.75 Ge 0.25 .
Lecture Notes in Computer Science, 2012
High supply voltage drops in a circuit may lead to significant performance degradation and even m... more High supply voltage drops in a circuit may lead to significant performance degradation and even malfunction in lower technology nodes like 45nm and below. Existing placement algorithms do not model voltage drops as an optimization objective and thus causes problems in power-integrity convergence. To remedy this deficiency, we propose a methodology to place the high power consumptions logic in lower IR (voltage) drop regions. We divide the whole floor plan into different buckets after doing an early voltage drop ...
IEEE Transactions on Electron Devices, 2007
This paper presents a new semianalytical model for the energy dispersion of the holes in the inve... more This paper presents a new semianalytical model for the energy dispersion of the holes in the inversion layer of pMOS transistors. The wave vector dependence of the energy inside the 2-D subbands is described with an analytical, nonparabolic, and anisotropic expression. The procedure to extract the parameters of the model is transparent and simple, and we have used the band structure obtained with the k • p method to calibrate the model for silicon MOSFETs with different crystal orientations. The model is validated by calculating several transport-related quantities in the inversion layer of a heavily doped pMOSFET and by systematically comparing the results to the corresponding k • p calculations. Finally, we have used the newly developed band-structure model to calculate the effective mobility of pMOS transistors and compare the results with the experimental data. The overall computational complexity of our model is dramatically smaller compared to a fully numerical treatment (such as the k • p method); hence, our approach opens new possibilities for the physically based modeling of pMOS transistors. Index Terms-Crystal orientations, hole mobility, inversion layer, modeling, pMOSFET, valence band structure. I. INTRODUCTION T HE CMOS technology is undergoing a generalized scaling strategy, where the strain engineering [1]-[4], the crystallographic orientation, and the use of alternative channel materials [5]-[11] are being evaluated as possible means to improve the transistor performance. Most of the aforementioned engineering knobs have been suggested on the basis of the experimentally observed mobility enhancements in long-Manuscript
IEEE Transactions on Electron Devices, 2006
This paper presents the first results and analysis of strained Si n-channel MOSFETs fabricated on... more This paper presents the first results and analysis of strained Si n-channel MOSFETs fabricated on thin SiGe virtual substrates. Significant improvements in electrical performance are demonstrated compared with Si control devices. The impact of SiGe device self-heating is compared for strained Si MOSFETs fabricated on thin and thick virtual substrates. This paper demonstrates that by using high-quality thin virtual substrates, the compromised performance enhancements commonly observed in short-gate-length MOSFETs and high-bias conditions due to selfheating in conventional thick virtual substrate devices are eradicated. The devices were fabricated with a 2.8-nm gate oxide and included NiSi to reduce the parasitic series resistance. The strained layers grown on the novel substrates comprising 20% Ge did not relax during fabrication. Good ON-state performance, OFF-state performance, and cross-wafer uniformity are demonstrated. The results show that thin virtual substrates have the potential to circumvent the major issues associated with conventional virtual substrate technology. A promising solution for realizing highperformance strained Si devices suitable for a wide range of applications is thus presented.
Earth, Moon, and Planets, 2012
The effects of 2009 Leonid Meteor Shower upon the two VLF subionospheric transmitted signals and ... more The effects of 2009 Leonid Meteor Shower upon the two VLF subionospheric transmitted signals and vertical electric potential gradient from the ground surface have been studied from Kolkata (Lat: 22.56°N, Long: 88.5°E) on November 17, 2009. The received signals showed their peak values when ZHR (Zenithal Hourly Rate) was highest. Some typical variations in the outcome of these measurements during the meteor showers will be presented in this paper.
ACS Applied Materials & Interfaces, 2013
High quality surface passivation on bulk-GaAs substrates and epitaxial-GaAs/Ge (epi-GaAs) layers ... more High quality surface passivation on bulk-GaAs substrates and epitaxial-GaAs/Ge (epi-GaAs) layers were achieved by using atomic layer deposited (ALD) titanium aluminum oxide (TiAlO) alloy dielectric. The TiAlO alloy dielectric suppresses the formation of defective native oxide on GaAs layers. X-ray photoelectron spectroscopy (XPS) analysis shows interfacial arsenic oxide (As(x)O(y)) and elemental arsenic (As) were completely removed from the GaAs surface. Energy dispersive X-ray diffraction (EDX) analysis and secondary ion mass spectroscopy (SIMS) analysis showed that TiAlO dielectric is an effective barrier layer for reducing the out-diffusion of elemental atoms, enhancing the electrical properties of bulk-GaAs based metal-oxide-semiconductor (MOS) devices. Moreover, ALD TiAlO alloy dielectric on epi-GaAs with AlGaAs buffer layer realized smooth interface between epi-GaAs layers and TiAlO dielectric, yielding a high quality surface passivation on epi-GaAs layers, much sought-after for high-speed transistor applications on a silicon platform. Presence of a thin AlGaAs buffer layer between epi-GaAs and Ge substrates improved interface quality and gate dielectric quality through the reduction of interfacial layer formation (Ga(x)O(y)) and suppression of elemental out-diffusion (Ga and As). The AlGaAs buffer layer and TiAlO dielectric play a key role to suppress the roughening, interfacial layer formation, and impurity diffusion into the dielectric, which in turn largely enhances the electrical property of the epi-GaAs MOS devices.
Nanoscale Research Letters, Feb 2, 2012
Electrical and physical properties of a metal-oxide-semiconductor [MOS] structure using atomic la... more Electrical and physical properties of a metal-oxide-semiconductor [MOS] structure using atomic layer-deposited high-k dielectrics (TiO 2 /Al 2 O 3) and epitaxial GaAs [epi-GaAs] grown on Ge(100) substrates have been investigated. The epi-GaAs, either undoped or Zn-doped, was grown using metal-organic chemical vapor deposition method at 620°C to 650°C. The diffusion of Ge atoms into epi-GaAs resulted in auto-doping, and therefore, an n-MOS behavior was observed for undoped and Zn-doped epi-GaAs with the doping concentration up to approximately 10 17 cm-3. This is attributed to the diffusion of a significant amount of Ge atoms from the Ge substrate as confirmed by the simulation using SILVACO software and also from the secondary ion mass spectrometry analyses. The Zn-doped epi-GaAs with a doping concentration of approximately 10 18 cm-3 converts the epi-GaAs layer into p-type since the Zn doping is relatively higher than the out-diffused Ge concentration. The capacitance-voltage characteristics show similar frequency dispersion and leakage current for n-type and p-type epi-GaAs layers with very low hysteresis voltage (approximately 10 mV).
arXiv (Cornell University), Oct 30, 2021
The current work investigates the performance of dual-gate GaAs-nanowire FET as a chargequbit dev... more The current work investigates the performance of dual-gate GaAs-nanowire FET as a chargequbit device operating at room temperature. In compatibility with the state-of-the-art classical bit technology, it is shown that the single gate of a nanowire FET can be replaced by two localized gates to achieve such charge-qubit operation. On application of relevant biases to the localized gates, two voltage tunable quantum dots are created within the nanowire channel with electrostatically controlled single-state-occupancy and inter-dot coupling leading to charge-qubit operation at room temperature. The associated electron transport is theoretically modeled on the basis of non-equilibrium Green's function (NEGF) formalism. The 'initialization' and 'manipulation' for qubit operation are performed by applying suitable gate voltages, whereas the 'measurement' is executed by applying a small drain bias to obtain a pulse current of ~pA order. A ~25 MHz frequency of coherent oscillation is observed for the qubit and a characteristic decay time of ~ 70 ns is achieved. The results suggest that such dual gate nanowire FET is a promising architecture for charge-qubit operation at room temperature.
Physical Review Applied, 2021
Applied Surface Science, 2017
Thin film of p-type cupric oxide (p-CuO) is grown on silicon (n-Si) substrate by using chemical b... more Thin film of p-type cupric oxide (p-CuO) is grown on silicon (n-Si) substrate by using chemical bath deposition (CBD) technique and a precise control of thickness from 60 nm to 178 nm has been achieved. The structural properties and stoichiometric composition of the grown films are observed to depend significantly on the growth time. The chemical composition, optical properties, and structural quality are investigated in detail by employing XRD, ellipsometric measurements and SEM images. Also, the elemental composition and the oxidation states of Cu and O in the grown samples have been studied in detail by XPS measurements. Thin film of 110 nm thicknesses exhibited the best performance in terms of crystal quality, refractive index, dielectric constant, band-gap, and optical properties. The study suggests synthesis route for developing high quality CuO thin film using CBD method for electronic and optical applications.
UV and Higher Energy Photonics: From Materials to Applications 2022
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Papers by Sanatan Chattopadhyay