Papers by Arnon Friedmann
IEEE Transactions on Magnetics, 2000
We propose a system for magnetic recording, using a low density parity check (LDPC) code as the e... more We propose a system for magnetic recording, using a low density parity check (LDPC) code as the error-correcting-code, in conjunction with a rate 16/17 quasi-maximum-transition-run channel code and a modified E 2 PR4-equalized channel. Iterative decoding between the partial response channel and the LDPC code is performed. Simulations show that this system can achieve a 5.9 dB gain over uncoded EPR4. The algorithms used to design this LDPC code are also discussed. Index Terms-Iterative decoding, low density parity check codes, magnetic recording.
Take a multicore Digital Signal Processor (DSP) chip designed for cellular base stations and radi... more Take a multicore Digital Signal Processor (DSP) chip designed for cellular base stations and radio network controllers, add floating-point capabilities to support 4G networks, and out of thin air a HPC engine is born. The potential for HPC is clear: It promises 128 GFLOPS (single precision) for 10 Watts; It is used in millions of network related devices and hence benefits from economies of scale; It should be simpler to program than a GPU. Simply put, it is fast, green, and cheap. But is it easy to use? In this paper, we show how this potential can be applied to general-purpose high performance computing, more specifically to dense matrix computations, without major changes in existing codes and methodologies, and with excellent performance and power consumption numbers.
1999 IEEE International Conference on Communications (Cat. No. 99CH36311)
Recent work on the application of turbo decoding techniques to partial response class 4 (PR4) cha... more Recent work on the application of turbo decoding techniques to partial response class 4 (PR4) channels has focused on parallel concatenation systems that require three APP detectors. A simplified serial concatenation system will be presented that uses as its outer code a single convolutional code and as its inner code the partial response channel. An extension of this serial concatenation system will also be presented that combines a second code with the channel, forming a more powerful inner code. Both proposed systems require only two APP detectors, offering significant savings in complexity and computation time. These serial concatenation systems will be shown to perform as well as the more complicated parallel concatenation systems, offering substantial gains over uncoded systems. Additionally, the effect of precoding will be investigated. Simulation results comparing the parallel and serial concatenation systems will be presented.
2012 International Conference for High Performance Computing, Networking, Storage and Analysis, 2012
Take a multicore Digital Signal Processor (DSP) chip designed for cellular base stations and radi... more Take a multicore Digital Signal Processor (DSP) chip designed for cellular base stations and radio network controllers, add floating-point capabilities to support 4G networks, and out of thin air a HPC engine is born. The potential for HPC is clear: It promises 128 GFLOPS (single precision) for 10 Watts; It is used in millions of network related devices and hence benefits from economies of scale; It should be simpler to program than a GPU. Simply put, it is fast, green, and cheap. But is it easy to use? In this paper, we show how this potential can be applied to general-purpose high performance computing, more specifically to dense matrix computations, without major changes in existing codes and methodologies, and with excellent performance and power consumption numbers. Index Terms-Low-power architectures, DSPs, linear algebra.
OpenMP in the Era of Low Power Devices and Accelerators, 2013
ABSTRACT The Texas Instrument (TI) Keystone II architecture integrates an octa-core C66X DSP with... more ABSTRACT The Texas Instrument (TI) Keystone II architecture integrates an octa-core C66X DSP with a quad-core ARM Cortex A15 MPCore processor in a non-cache coherent shared memory environment. This System-on-a-Chip (SoC) offers very high Floating Point Operations per second (FLOPS) per Watt, if used efficiently. This paper reports an initial attempt at developing a bare-metal OpenMP runtime for the C66X multi-core DSP using the Open Event Machine RTOS. It also outlines an extension to OpenMP that allows code to run across both the ARM and the DSP cores simultaneously. Preliminary performance data for OpenMP constructs running on the ARM and DSP parts of the SoC are given and compared with other current processors.
IEEE Transactions on Magnetics, 1996
In this work we design a sliding threshold implementation of a Viterbi detector for a ternary 1-D... more In this work we design a sliding threshold implementation of a Viterbi detector for a ternary 1-D recording channel. We show that the final detection scheme is both simple and easy to implement in analog fashion, much like the binary equivalent.
IEEE Transactions on Magnetics, 1995
Overwrite in tape recording is studied by three dimensional micromagnetic simuIation. We simulate... more Overwrite in tape recording is studied by three dimensional micromagnetic simuIation. We simulate thick tape media of randomly distributed ellipsoidal particles with proper orientation distributions. Our initial calculations examine the overwriting of a low frequency NEZI signal by a higher frequency signal. The simulation allows us to look at the signal spectrum at each depth into the medium before and after overwrite. We And that the residual low frequency signal is due to contributions from all depths in the media. The effect of record equalization on overwrite ratios is also studied.
Typical forward error correction methods employ Trellis Code Modulation. By substituting low dens... more Typical forward error correction methods employ Trellis Code Modulation. By substituting low density parity check coding in place of the convolution code as part of a combined modulation and encoding procedure, low density parity check coding and modulation can be performed. The low density parity check codes have no error floor, no cycles, an equal bit error rate for the information bits and the parity bits, and timely construction of both a parity check matrix with variable codeword size and a generator matrix is possible.
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Papers by Arnon Friedmann