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Insights: intel/rohd
Overview
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- 1 Merged pull request
- 0 Open pull requests
- 2 Closed issues
- 7 New issues
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1 Pull request merged by 1 person
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Fix bug in
LogicStructure.previousValue
#565 merged
Feb 20, 2025
2 Issues closed by 1 person
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Waveform signals do not match generated RTL
#572 closed
Feb 26, 2025 -
Allow ints&bools to be used in operators,eq,neq,etc
#573 closed
Feb 26, 2025
7 Issues opened by 2 people
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WaveDumper outputs empty file when test() {expect()} fails
#574 opened
Feb 26, 2025 -
Add `State.ssa` to enable SSA in `FiniteStateMachine`
#571 opened
Feb 25, 2025 -
Waveform shows 'x' when driving signal with 'z'
#570 opened
Feb 25, 2025 -
Improve error message of `Signal changed its value after ...`
#569 opened
Feb 25, 2025 -
Add an example of `ExternalSystemVerilogModule` to the user guide
#568 opened
Feb 25, 2025 -
SimpleClockGenerator doesnt work with period of 1
#567 opened
Feb 25, 2025 -
Limit length of generated signal names
#566 opened
Feb 20, 2025
2 Unresolved conversations
Sometimes conversations happen on old items that aren’t yet closed. Here is a list of all the Issues and Pull Requests with unresolved conversations.
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"Default" values for `FiniteStateMachine`s
#509 commented on
Feb 25, 2025 • 0 new comments -
Add the ability to configure WaveDumper to ignore internal signals
#323 commented on
Feb 26, 2025 • 0 new comments