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WaveDumper outputs empty file when test() {expect()} fails
bug
Something isn't working
#574
opened Feb 26, 2025 by
awmoore-intel
Add New feature or request
help wanted
Extra attention is needed
State.ssa
to enable SSA in FiniteStateMachine
enhancement
#571
opened Feb 25, 2025 by
mkorbel1
Waveform shows 'x' when driving signal with 'z'
bug
Something isn't working
#570
opened Feb 25, 2025 by
awmoore-intel
Improve error message of New feature or request
Signal changed its value after ...
enhancement
#569
opened Feb 25, 2025 by
awmoore-intel
Add an example of Improvements or additions to documentation
enhancement
New feature or request
good first issue
Good for newcomers
ExternalSystemVerilogModule
to the user guide
documentation
#568
opened Feb 25, 2025 by
mkorbel1
SimpleClockGenerator doesnt work with period of 1
bug
Something isn't working
help wanted
Extra attention is needed
#567
opened Feb 25, 2025 by
awmoore-intel
Limit length of generated signal names
enhancement
New feature or request
help wanted
Extra attention is needed
#566
opened Feb 20, 2025 by
mkorbel1
Make assignments between packed LogicArrays and Logics in generated SystemVerilog avoid a swizzle
enhancement
New feature or request
help wanted
Extra attention is needed
#559
opened Jan 29, 2025 by
mkorbel1
Add WASM compiliation support
enhancement
New feature or request
help wanted
Extra attention is needed
#554
opened Jan 21, 2025 by
mkorbel1
Resolve driver vs. receiver based on usage for certain types of operations
enhancement
New feature or request
#553
opened Jan 21, 2025 by
mkorbel1
Omit redundant parentheses in generated SystemVerilog
enhancement
New feature or request
help wanted
Extra attention is needed
#552
opened Jan 21, 2025 by
mkorbel1
Mark bit ranges in swizzles in generated SystemVerilog
enhancement
New feature or request
good first issue
Good for newcomers
#551
opened Jan 21, 2025 by
mkorbel1
Attaching a packed array port to an unpacked array port of a submodule generates bad SV
bug
Something isn't working
help wanted
Extra attention is needed
#549
opened Jan 15, 2025 by
mkorbel1
Add optional source annotation in generated outputs
enhancement
New feature or request
#547
opened Jan 15, 2025 by
mkorbel1
Mark dangling ports in module instantiations
enhancement
New feature or request
help wanted
Extra attention is needed
#546
opened Jan 15, 2025 by
mkorbel1
Automatic sorting and grouping for generated outputs
enhancement
New feature or request
help wanted
Extra attention is needed
#545
opened Jan 15, 2025 by
mkorbel1
Error when sub-modules are already built is confusing
enhancement
New feature or request
#544
opened Jan 15, 2025 by
mkorbel1
Allow swizzles to be receivers of assignments in generated SystemVerilog for nets
enhancement
New feature or request
#530
opened Nov 22, 2024 by
mkorbel1
Consts that Something isn't working
help wanted
Extra attention is needed
inferWidth
to 0-width generate SystemVerilog with 0-width
bug
#527
opened Oct 14, 2024 by
mkorbel1
Add documentation on Improvements or additions to documentation
enhancement
New feature or request
help wanted
Extra attention is needed
Interface
s driving/receiving each other
documentation
#524
opened Oct 4, 2024 by
mkorbel1
Allow swizzling on New feature or request
good first issue
Good for newcomers
Iterable
instead of just List
enhancement
#523
opened Oct 4, 2024 by
mkorbel1
When replicating by 1, just return the 1 signal
enhancement
New feature or request
good first issue
Good for newcomers
#522
opened Oct 4, 2024 by
mkorbel1
Add documentation for Improvements or additions to documentation
enhancement
New feature or request
good first issue
Good for newcomers
selectIndex
and selectFrom
in the user guide
documentation
#520
opened Oct 4, 2024 by
mkorbel1
PairInterface
cloning should include subInterfaces
as well
enhancement
#519
opened Oct 4, 2024 by
mkorbel1
Expose & infer New feature or request
good first issue
Good for newcomers
name
on automations like flop
, cases
, mux
, etc.
enhancement
#517
opened Oct 3, 2024 by
mkorbel1
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