This paper presents a method for designing SystemCcompliant Instruction Set Simulators (ISS) that... more This paper presents a method for designing SystemCcompliant Instruction Set Simulators (ISS) that address three of the major problems system designers are faced with when modeling MP-SoCs architectures: the multiple levels of abstraction of the simulation models supporting the design space exploration, the simulation speed, and the debug of the multithreaded embedded application. First, this paper presents the ISS API and principles; then it describes how the same ISS can support SystemC simulation at several abstraction levels: untimed transaction level, approximately timed transaction level, and cycle accurate; then, it describes how the proposed ISS API has been used by six different laboratories -in the framework of the SoCLib project -to share the same L1 cache simulation model, and to wrap seven different processor cores in the same generic wrappers. Finally we demonstrate how the proposed API has been exploited to develop a generic debug and instrumentation infrastructure that can be used for all the processor cores, and all the abstraction levels supported by the SoCLib virtual prototyping platform.
Simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs... more Simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs). SystemC TLM2.0 (Transaction Level Modeling) is now commonly used to accelerate the simulation. However, the standard SystemC simulation engine uses a centralized scheduler that is clearly a bottleneck to parallelize the simulation of architectures containing hundreds of processor cores, and involving hundreds of SC_THREADs to
We compared the effectiveness of alcohol gel with that of the traditional hand-cleansing agents i... more We compared the effectiveness of alcohol gel with that of the traditional hand-cleansing agents in removing clinical strains of Acinetobacter baumannii, methicillin-resistant Staphylococcus aureus, Escherichia coli, Enterococcus faecalis, Pseudomonas aeruginosa, and Candida albicans from artificially contaminated hands. The fingertips of 6 volunteers were contaminated with approximately 10 6 of microbial cells, and then were washed with: plain liquid soap, alcohol gel, 70% ethyl alcohol (by weight), 10% povidone-iodine liquid soap (PVP-I), and 4% chlorhexidine gluconate detergent. The experiments were performed using a Latin square statistical design, with six 6 x 5 randomized blocks, and the results were estimated by ANOVA. The products reduced from 93.83% (plain liquid soap) to 100% (PVP-I) of the microbial population applied to the hands. In 4 of 6 test microorganisms analyzed, 10% PVP-I, alcohol gel, 70% ethyl alcohol, and 4% chlorhexidine had significantly higher removal rates than plain liquid soap (P < 0.05). The results confirm the effectiveness of alcohol gel for hand hygiene and suggest that 10% PVP-I, alcohol gel, 70% ethyl alcohol, and 4% chlorhexidine may be more effective than plain liquid soap for removing A. baumannii, E. coli, E. faecalis, and C. albicans strains from heavily contaminated hands.
The network on chip (NoC) design process requires an adequate characterization of the application... more The network on chip (NoC) design process requires an adequate characterization of the application running on it to optimize communication resources utilization and dimensioning. The traffic modeling process is the most essential step for characterizing complex applications. It is possible to identify three methods to model traffic in NoC literature. The first one assumes sources continually send data at a constant rate to the network and it is the most commonly used. The second method employs probabilistic functions to model the traffic behavior for typical applications, as audio and video streams. The accuracy of this method is better, at the extra cost of modeling complexity and simulation time. The third method employs traffic traces to evaluate network performance. Even with small traces, simulation time can be prohibitive. The advantage is accuracy, superior to the previous models. Even if a given application is correctly modeled, other flows interfere on how the application traffic behaves within the network. Results about the mutual interference of different traffic flows in NoCs are scarce. This work has two main objectives: (i) compare NoC performance, in terms of throughput and latency, when different traffic models are used for the same application; (ii) evaluate the impact of network noise traffic on some specific modeled flow. Preliminary results show how far is the real NoC performance for a given application when an oversimplified model is employed. The conclusion is that NoCs must employ internal mechanisms to ensure QoS, since noise traffic makes modeled traffic to depart from its predicted behavior.
Several propositions of NoC architectures claim providing quality of service (QoS) guarantees, wh... more Several propositions of NoC architectures claim providing quality of service (QoS) guarantees, which is essential for e.g. real time and multimedia applications. The state-of-art in NoC literature provides QoS at design time, using circuit switching and/or priority-based scheduling. Both methods optimize a given network template to achieve the QoS requirements after traffic generation and network simulation. However, modern SoCs may execute applications not devised at design time, and these may easily have its QoS requirements violated by a previously fixed NoC structure. This paper proposes a method to achieve QoS requirements in NoCs at execution time. The proposed rate-based scheduling policy is employed to determine the priority of each QoS flow being transmitted through the network. The basis of this scheduling method is the difference between the rate required by a given flow and the rate currently used by this flow. This difference corresponds to the flow priority used by the scheduler. Differently from traditional priority-based scheduling, the priority is dynamically adjusted. Preliminary results show the efficiency of the rate-based scheduling to meet QoS requirements, by comparing the proposed scheduling to priority-based scheduling.
The increasing complexity of integrated circuits drives the research of new on-chip interconnecti... more The increasing complexity of integrated circuits drives the research of new on-chip interconnection architectures. Networks-on-chip (NoCs) are a candidate architecture to be used in future systems, due to its increased performance, reusability and scalability. A NoC is a set of interconnected switches, with IP cores connected to these switches. Four main components compose a switch: a router, to define a path between input and output switch ports; an arbiter, to grant access to a given port when multiple input requests arrive in parallel; buffers, to store intermediate data, and a flow control module to regulate the data transfer to the next switch. The goal of this work is to compare the performance of four routing algorithms for mesh based packet switching NoCs. Differently from the literature for generic networks, it is shown that deterministic algorithms can be superior to adaptive ones in NoCs.
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an ... more The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed interconnection structure is a Network on Chip, or NoC. NoCs are emerging as a viable alternative to increasing demands on interconnection architectures, due to the following characteristics: (i) energy efficiency and reliability; (ii) scalability of bandwidth, when compared to traditional bus architectures; (iii) reusability; (iv) distributed routing decisions. An external host computer feeds MultiNoC with application instructions and data. After this initialization procedure, MultiNoC executes some algorithm. After finishing execution of the algorithm, output data can be read back by the host. Sequential or parallel algorithms conveniently adapted to the MultiNoC structure can be executed. The main motivation to propose this design is to enable the investigation of current trends to increase the number of embedded processors in SoCs, leading to the concept of "sea of processors" systems.
The MultiNoC system implements a programmable on-chip multiprocessing platform built on top of an... more The MultiNoC system implements a programmable on-chip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed interconnection structure is a Network on Chip, or NoC. NoCs are emerging as a viable alternative to increasing demands on interconnection architectures, due to the following characteristics: (i) energy efficiency and reliability; (ii) scalability of bandwidth, when compared to traditional bus architectures; (iii) reusability; (iv) distributed routing decisions. An external host computer feeds MultiNoC with application instructions and data. After this initialization procedure, MultiNoC executes some algorithm. After finishing execution of the algorithm, output data can be read back by the host. Sequential or parallel algorithms conveniently adapted to the MultiNoC structure can be executed. The main motivation to propose this design is to enable the investigation of current trends to increase the number of embedded processors in SoCs, leading to the concept of "sea of processors" systems.
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an ... more The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed interconnection structure is a Network on Chip, or NoC. NoCs are emerging as a viable alternative to increasing demands on interconnection architectures, due to the following characteristics: (i) energy efficiency and reliability; (ii) scalability of bandwidth, when compared to traditional bus architectures; (iii) reusability; (iv) distributed routing decisions. An external host computer feeds MultiNoC with application instructions and data. After this initialization procedure, MultiNoC executes some algorithm. After finishing execution of the algorithm, output data can be read back by the host. Sequential or parallel algorithms conveniently adapted to the MultiNoC structure can be executed. The main motivation to propose this design is to enable the investigation of current trends to increase the number of embedded processors in SoCs, leading to the concept of "sea of processors" systems.
one communication architecture candidate to be used in present and futures SoCs, due to its scala... more one communication architecture candidate to be used in present and futures SoCs, due to its scalability, reusability and performance. The focus of this paper is the analysis of IP communication models in NoCs. Employing standard external interfaces, as OCP, is recommended to enable the use of NoCs by different IP core providers. The second point related to reusability is the IP cores communication model. Two basic communication models are considered in this work: NUMA and NORMA. The goal of this work is to evaluate the pros and cons of each communication model, in terms of network interface complexity, area and performance.
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks... more Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congestion in NoCs reduces the overall system performance. This effect is particularly strong in networks where a single buffer is associated with each input channel, which simplifies router design, but prevents packets from sharing a physical channel at any given instant of time. The goal of this work is to describe the implementation of a mechanism to reduce performance penalization due to packet concurrence for network resources in NoCs. One way to reduce congestion is to multiplex a physical channel using virtual channels (VCs). VCs reduce latency and increase network throughput. The insertion of VCs also enables to implement policies for allocating the physical channel bandwidth, which enables to support quality of service (QoS) in applications. This paper has two main contributions. The first is the detailed implementation of a NoC router with a parameterizable number of VCs. The second is the evaluation of latency and throughput in reasonably sized instances of the Hermes NoC (8x8 mesh), with and without VCs. Additionally, the paper compares the features of the proposed router with others employing VCs. Results show that NoCs with VCs accept higher injections rates w.r.t. NoCs without VCs, with a small standard deviation in the latency values, guaranteeing precise packet latency estimation.
The use of pre-designed and pre-verified complex hardware modules, also called IP cores, is an im... more The use of pre-designed and pre-verified complex hardware modules, also called IP cores, is an important part of the effort to design and implement complex systems. However, many aspects of IP core manipulation are still to be developed. This paper presents an approach to solve problems related to the dynamic interconnection of hard IP cores inside VLSI reconfigurable devices. The approach targets system-on-a-chip designs built in a single large FPGA. The paper proposes a communication interface that allows IP cores replacement during FPGA normal operation. The same interface also allows the communication among distinct IP cores to take place.
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) n... more The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these methods have to address are the generation and evaluation of network traffic. Traffic generation allows injecting packets in the network according to application constraint specifications such as transmission rate and end-to-end latency. Performance evaluation helps in computing latency and throughput at network channels/interfaces, as well as to identify congestion and hotspots. This paper reviews related works in traffic generation and performance evaluation for mesh topology NoCs, and proposes general methods for both aspects. Three parameters are used here to define traffic generation: packet spatial distribution, packet injection rate and packet size. Two types of methods to evaluate performance in NoCs are discussed: (i) external evaluation, a common strategy found in related works, where the network is considered as a black box and traffic results are obtained only from the external network interfaces; (ii) internal evaluation, where performance is computed in each network channel. The paper presents the result of experiments conducted in an 8x8 mesh network, varying the routing algorithms and the number of virtual channels. The main contribution of this work is the set of methods for internal NoC evaluation, which help designers to optimize the network under different traffic scenarios.
The increasing complexity of integrated circuits drives the research of new on-chip interconnecti... more The increasing complexity of integrated circuits drives the research of new on-chip interconnection architectures. A network on chip draws on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. The main goal pursued is to achieve superior bandwidth when compared to conventional on-chip bus architectures. This paper reviews the state of the art in networks on chip. Then, it describes an infrastructure called Hermes, targeted to implement packet-switching mesh and related interconnection architectures and topologies. The basic element of Hermes is a switch with five bi-directional ports, connecting to four other switches and to a local IP core. The switch employs an XY routing algorithm, and uses input queuing. The main design objective was to develop a small size switch, enabling its immediate practical use. The paper also presents the design validation of the Hermes switch and of a network on chip based on it. A Hermes NoC case study has been successfully prototyped in hardware as described in the paper, demonstrating the functionality of the approach. Quantitative data for the Hermes infrastructure is advanced. r
The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses ... more The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be developed to integrate NoC interconnection architectures and IP cores into SoCs. Such tools have to fulfill three main requirements: (i) automated NoC generation; (ii) automated production of NoC-IP core interfaces; (iii) seamless analysis of NoC traffic parameters. The objective of this paper is to present the MAIA framework, which includes functions to address all these requirements. NoCs generated by the MAIA framework have been used to successfully prototype SoCs in FPGAs.
Abstract The increasing complexity of integrated circuits drives the research of new intra-chip i... more Abstract The increasing complexity of integrated circuits drives the research of new intra-chip interconnection architectures. A network-on-chip adapts concepts originated in the distributed systems and computer networks subject areas to connect IP cores in a structured and scalable way, pursuing the goal of achieving superior bandwidth to conventional intra-chip bus architectures. This paper presents the design of a switch targeted to a mesh interconnection topology. Each switch has 5 bi-directional ports, connecting 4 neighbor ...
bibliografia básica utilizada: CHAUÍ, Marilena. Convite à filosofia. 13ª ed. São Paulo: Ática, 20... more bibliografia básica utilizada: CHAUÍ, Marilena. Convite à filosofia. 13ª ed. São Paulo: Ática, 2004. MARCONDES, Danilo. Iniciação à história da filosofia: dos pré-socráticos a Wittgenstein. 10ª ed. Rio de Janeiro: Jorge Zahar Ed., 2006. Exposição: -A importância das disciplinas propedêuticas: Agora é hora de vender meu peixe. Para que filosofia? Entrei no curso de Direito. Quero aprender a tirar o ladrão da prisão. Quero conseguir que o titio, que está preso há um mês porque não paga pensão alimentícia seja solto.
This paper presents a method for designing SystemCcompliant Instruction Set Simulators (ISS) that... more This paper presents a method for designing SystemCcompliant Instruction Set Simulators (ISS) that address three of the major problems system designers are faced with when modeling MP-SoCs architectures: the multiple levels of abstraction of the simulation models supporting the design space exploration, the simulation speed, and the debug of the multithreaded embedded application. First, this paper presents the ISS API and principles; then it describes how the same ISS can support SystemC simulation at several abstraction levels: untimed transaction level, approximately timed transaction level, and cycle accurate; then, it describes how the proposed ISS API has been used by six different laboratories -in the framework of the SoCLib project -to share the same L1 cache simulation model, and to wrap seven different processor cores in the same generic wrappers. Finally we demonstrate how the proposed API has been exploited to develop a generic debug and instrumentation infrastructure that can be used for all the processor cores, and all the abstraction levels supported by the SoCLib virtual prototyping platform.
Simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs... more Simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs). SystemC TLM2.0 (Transaction Level Modeling) is now commonly used to accelerate the simulation. However, the standard SystemC simulation engine uses a centralized scheduler that is clearly a bottleneck to parallelize the simulation of architectures containing hundreds of processor cores, and involving hundreds of SC_THREADs to
We compared the effectiveness of alcohol gel with that of the traditional hand-cleansing agents i... more We compared the effectiveness of alcohol gel with that of the traditional hand-cleansing agents in removing clinical strains of Acinetobacter baumannii, methicillin-resistant Staphylococcus aureus, Escherichia coli, Enterococcus faecalis, Pseudomonas aeruginosa, and Candida albicans from artificially contaminated hands. The fingertips of 6 volunteers were contaminated with approximately 10 6 of microbial cells, and then were washed with: plain liquid soap, alcohol gel, 70% ethyl alcohol (by weight), 10% povidone-iodine liquid soap (PVP-I), and 4% chlorhexidine gluconate detergent. The experiments were performed using a Latin square statistical design, with six 6 x 5 randomized blocks, and the results were estimated by ANOVA. The products reduced from 93.83% (plain liquid soap) to 100% (PVP-I) of the microbial population applied to the hands. In 4 of 6 test microorganisms analyzed, 10% PVP-I, alcohol gel, 70% ethyl alcohol, and 4% chlorhexidine had significantly higher removal rates than plain liquid soap (P < 0.05). The results confirm the effectiveness of alcohol gel for hand hygiene and suggest that 10% PVP-I, alcohol gel, 70% ethyl alcohol, and 4% chlorhexidine may be more effective than plain liquid soap for removing A. baumannii, E. coli, E. faecalis, and C. albicans strains from heavily contaminated hands.
The network on chip (NoC) design process requires an adequate characterization of the application... more The network on chip (NoC) design process requires an adequate characterization of the application running on it to optimize communication resources utilization and dimensioning. The traffic modeling process is the most essential step for characterizing complex applications. It is possible to identify three methods to model traffic in NoC literature. The first one assumes sources continually send data at a constant rate to the network and it is the most commonly used. The second method employs probabilistic functions to model the traffic behavior for typical applications, as audio and video streams. The accuracy of this method is better, at the extra cost of modeling complexity and simulation time. The third method employs traffic traces to evaluate network performance. Even with small traces, simulation time can be prohibitive. The advantage is accuracy, superior to the previous models. Even if a given application is correctly modeled, other flows interfere on how the application traffic behaves within the network. Results about the mutual interference of different traffic flows in NoCs are scarce. This work has two main objectives: (i) compare NoC performance, in terms of throughput and latency, when different traffic models are used for the same application; (ii) evaluate the impact of network noise traffic on some specific modeled flow. Preliminary results show how far is the real NoC performance for a given application when an oversimplified model is employed. The conclusion is that NoCs must employ internal mechanisms to ensure QoS, since noise traffic makes modeled traffic to depart from its predicted behavior.
Several propositions of NoC architectures claim providing quality of service (QoS) guarantees, wh... more Several propositions of NoC architectures claim providing quality of service (QoS) guarantees, which is essential for e.g. real time and multimedia applications. The state-of-art in NoC literature provides QoS at design time, using circuit switching and/or priority-based scheduling. Both methods optimize a given network template to achieve the QoS requirements after traffic generation and network simulation. However, modern SoCs may execute applications not devised at design time, and these may easily have its QoS requirements violated by a previously fixed NoC structure. This paper proposes a method to achieve QoS requirements in NoCs at execution time. The proposed rate-based scheduling policy is employed to determine the priority of each QoS flow being transmitted through the network. The basis of this scheduling method is the difference between the rate required by a given flow and the rate currently used by this flow. This difference corresponds to the flow priority used by the scheduler. Differently from traditional priority-based scheduling, the priority is dynamically adjusted. Preliminary results show the efficiency of the rate-based scheduling to meet QoS requirements, by comparing the proposed scheduling to priority-based scheduling.
The increasing complexity of integrated circuits drives the research of new on-chip interconnecti... more The increasing complexity of integrated circuits drives the research of new on-chip interconnection architectures. Networks-on-chip (NoCs) are a candidate architecture to be used in future systems, due to its increased performance, reusability and scalability. A NoC is a set of interconnected switches, with IP cores connected to these switches. Four main components compose a switch: a router, to define a path between input and output switch ports; an arbiter, to grant access to a given port when multiple input requests arrive in parallel; buffers, to store intermediate data, and a flow control module to regulate the data transfer to the next switch. The goal of this work is to compare the performance of four routing algorithms for mesh based packet switching NoCs. Differently from the literature for generic networks, it is shown that deterministic algorithms can be superior to adaptive ones in NoCs.
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an ... more The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed interconnection structure is a Network on Chip, or NoC. NoCs are emerging as a viable alternative to increasing demands on interconnection architectures, due to the following characteristics: (i) energy efficiency and reliability; (ii) scalability of bandwidth, when compared to traditional bus architectures; (iii) reusability; (iv) distributed routing decisions. An external host computer feeds MultiNoC with application instructions and data. After this initialization procedure, MultiNoC executes some algorithm. After finishing execution of the algorithm, output data can be read back by the host. Sequential or parallel algorithms conveniently adapted to the MultiNoC structure can be executed. The main motivation to propose this design is to enable the investigation of current trends to increase the number of embedded processors in SoCs, leading to the concept of "sea of processors" systems.
The MultiNoC system implements a programmable on-chip multiprocessing platform built on top of an... more The MultiNoC system implements a programmable on-chip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed interconnection structure is a Network on Chip, or NoC. NoCs are emerging as a viable alternative to increasing demands on interconnection architectures, due to the following characteristics: (i) energy efficiency and reliability; (ii) scalability of bandwidth, when compared to traditional bus architectures; (iii) reusability; (iv) distributed routing decisions. An external host computer feeds MultiNoC with application instructions and data. After this initialization procedure, MultiNoC executes some algorithm. After finishing execution of the algorithm, output data can be read back by the host. Sequential or parallel algorithms conveniently adapted to the MultiNoC structure can be executed. The main motivation to propose this design is to enable the investigation of current trends to increase the number of embedded processors in SoCs, leading to the concept of "sea of processors" systems.
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an ... more The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed interconnection structure is a Network on Chip, or NoC. NoCs are emerging as a viable alternative to increasing demands on interconnection architectures, due to the following characteristics: (i) energy efficiency and reliability; (ii) scalability of bandwidth, when compared to traditional bus architectures; (iii) reusability; (iv) distributed routing decisions. An external host computer feeds MultiNoC with application instructions and data. After this initialization procedure, MultiNoC executes some algorithm. After finishing execution of the algorithm, output data can be read back by the host. Sequential or parallel algorithms conveniently adapted to the MultiNoC structure can be executed. The main motivation to propose this design is to enable the investigation of current trends to increase the number of embedded processors in SoCs, leading to the concept of "sea of processors" systems.
one communication architecture candidate to be used in present and futures SoCs, due to its scala... more one communication architecture candidate to be used in present and futures SoCs, due to its scalability, reusability and performance. The focus of this paper is the analysis of IP communication models in NoCs. Employing standard external interfaces, as OCP, is recommended to enable the use of NoCs by different IP core providers. The second point related to reusability is the IP cores communication model. Two basic communication models are considered in this work: NUMA and NORMA. The goal of this work is to evaluate the pros and cons of each communication model, in terms of network interface complexity, area and performance.
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks... more Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congestion in NoCs reduces the overall system performance. This effect is particularly strong in networks where a single buffer is associated with each input channel, which simplifies router design, but prevents packets from sharing a physical channel at any given instant of time. The goal of this work is to describe the implementation of a mechanism to reduce performance penalization due to packet concurrence for network resources in NoCs. One way to reduce congestion is to multiplex a physical channel using virtual channels (VCs). VCs reduce latency and increase network throughput. The insertion of VCs also enables to implement policies for allocating the physical channel bandwidth, which enables to support quality of service (QoS) in applications. This paper has two main contributions. The first is the detailed implementation of a NoC router with a parameterizable number of VCs. The second is the evaluation of latency and throughput in reasonably sized instances of the Hermes NoC (8x8 mesh), with and without VCs. Additionally, the paper compares the features of the proposed router with others employing VCs. Results show that NoCs with VCs accept higher injections rates w.r.t. NoCs without VCs, with a small standard deviation in the latency values, guaranteeing precise packet latency estimation.
The use of pre-designed and pre-verified complex hardware modules, also called IP cores, is an im... more The use of pre-designed and pre-verified complex hardware modules, also called IP cores, is an important part of the effort to design and implement complex systems. However, many aspects of IP core manipulation are still to be developed. This paper presents an approach to solve problems related to the dynamic interconnection of hard IP cores inside VLSI reconfigurable devices. The approach targets system-on-a-chip designs built in a single large FPGA. The paper proposes a communication interface that allows IP cores replacement during FPGA normal operation. The same interface also allows the communication among distinct IP cores to take place.
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) n... more The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these methods have to address are the generation and evaluation of network traffic. Traffic generation allows injecting packets in the network according to application constraint specifications such as transmission rate and end-to-end latency. Performance evaluation helps in computing latency and throughput at network channels/interfaces, as well as to identify congestion and hotspots. This paper reviews related works in traffic generation and performance evaluation for mesh topology NoCs, and proposes general methods for both aspects. Three parameters are used here to define traffic generation: packet spatial distribution, packet injection rate and packet size. Two types of methods to evaluate performance in NoCs are discussed: (i) external evaluation, a common strategy found in related works, where the network is considered as a black box and traffic results are obtained only from the external network interfaces; (ii) internal evaluation, where performance is computed in each network channel. The paper presents the result of experiments conducted in an 8x8 mesh network, varying the routing algorithms and the number of virtual channels. The main contribution of this work is the set of methods for internal NoC evaluation, which help designers to optimize the network under different traffic scenarios.
The increasing complexity of integrated circuits drives the research of new on-chip interconnecti... more The increasing complexity of integrated circuits drives the research of new on-chip interconnection architectures. A network on chip draws on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. The main goal pursued is to achieve superior bandwidth when compared to conventional on-chip bus architectures. This paper reviews the state of the art in networks on chip. Then, it describes an infrastructure called Hermes, targeted to implement packet-switching mesh and related interconnection architectures and topologies. The basic element of Hermes is a switch with five bi-directional ports, connecting to four other switches and to a local IP core. The switch employs an XY routing algorithm, and uses input queuing. The main design objective was to develop a small size switch, enabling its immediate practical use. The paper also presents the design validation of the Hermes switch and of a network on chip based on it. A Hermes NoC case study has been successfully prototyped in hardware as described in the paper, demonstrating the functionality of the approach. Quantitative data for the Hermes infrastructure is advanced. r
The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses ... more The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be developed to integrate NoC interconnection architectures and IP cores into SoCs. Such tools have to fulfill three main requirements: (i) automated NoC generation; (ii) automated production of NoC-IP core interfaces; (iii) seamless analysis of NoC traffic parameters. The objective of this paper is to present the MAIA framework, which includes functions to address all these requirements. NoCs generated by the MAIA framework have been used to successfully prototype SoCs in FPGAs.
Abstract The increasing complexity of integrated circuits drives the research of new intra-chip i... more Abstract The increasing complexity of integrated circuits drives the research of new intra-chip interconnection architectures. A network-on-chip adapts concepts originated in the distributed systems and computer networks subject areas to connect IP cores in a structured and scalable way, pursuing the goal of achieving superior bandwidth to conventional intra-chip bus architectures. This paper presents the design of a switch targeted to a mesh interconnection topology. Each switch has 5 bi-directional ports, connecting 4 neighbor ...
bibliografia básica utilizada: CHAUÍ, Marilena. Convite à filosofia. 13ª ed. São Paulo: Ática, 20... more bibliografia básica utilizada: CHAUÍ, Marilena. Convite à filosofia. 13ª ed. São Paulo: Ática, 2004. MARCONDES, Danilo. Iniciação à história da filosofia: dos pré-socráticos a Wittgenstein. 10ª ed. Rio de Janeiro: Jorge Zahar Ed., 2006. Exposição: -A importância das disciplinas propedêuticas: Agora é hora de vender meu peixe. Para que filosofia? Entrei no curso de Direito. Quero aprender a tirar o ladrão da prisão. Quero conseguir que o titio, que está preso há um mês porque não paga pensão alimentícia seja solto.
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