Dimming light idea

Question

I have this idea to dim a light. The problem is that my EBS simulation software won't allow me to see the actual result of the dimming. The only way to test it out is to physically construct the circuit.

My idea is that after a zero-cross has been detected, the upper-most 555 timer should turn on. This should turn the TRIAC on and off with a duty cycle of 60% and hence reduce the brightness by the very same amount. The lower 555 timer basically turns on the light and variable periods with varying duty cycles.

Will this work? Is there a better way or improvement that someone can suggest? Note, I'm doing this strictly using fundamental analog/digital design, so no fancy Raspberry Pis, Arduinos, and all that jazz.

One more thing, that can be noted from the diagram is that the dimming only occurs when the "LDR daylight detector is on."

Answer 1

This should turn the triac on and off with a duty cycle of 60%

Triacs turn off when their main current falls below a threshold. In other words, you can turn on a triac from a control pin but, you can't turn it off with that control pin immediately. If you deactivate the control pin, the triac will stay activated until the main current flow reduces to near zero (normally this happens at the zero cross of the AC mains.

But will this work?

Not as far as I can see.

Is there a better way or improvement that someone can suggest?

Normal light dimmers operate by turning the triac on at a point in time with respect to the subsequent zero cross i.e. they are synchronized to the AC mains. I suggest you take this route.

The problem is that my EBS simulation software won't allow me to see the actual result of the dimming.

I can only advise you to adopt a better simulation tool.

Answer 2

strictly using fundamental analog/digital design, so no fancy Raspberry Pis, Arduinos, and all that jazz.

A simple MCU would yield the lowest absolute component count, and would teach you a lot of fundamentals.

Without an MCU, you'll be using discrete semiconductor digital devices. A DIAC and a TRIAC are the ultimate digital building blocks - very robust, work directly from high supply voltages, and so on.

A DIAC is a S/#R latch with S connected to MT1, and #R connected differentially across MT1 and MT2.

A TRIAC is a S/#R latch with the S input called "gate", and #R is a differential input connected between BT1 and BT2.

Also, both the DIAC and the TRIAC treat positive and negative voltages relative one MT terminal as high logic state, and 0V relative to that same MT terminal as low state.

I have this idea to dim a light.

The execution is a wee bit complex for what little the circuit does. What you want is more-or-less a dusk-dawn light circuit, but with the light not fully turned off. You can just look one of those up and see how to modify it to do partial dimming vs. full-off.

What we want is, in principle:

1. LDR-controlled source of a binary signal with two states FULL and DIMMED.

2. A dimmer circuit that is either continuously on, or partially on, based on the binary control signal.

As a clean-slate design, the circuit below does it.

The dashed netlists on the bottom are simulation models of the TRIAC (left) and the DIAC (right). They are only there because CircuitLab, similarly to very old SPICE programs (from the times of punched cards and such) doesn't include diacs and triacs. The components inside the dashed lines each represent a line from the subcircuit deck, and a bit over half a century ago would have been on a punched card each :)

On the top we have the main circuit. On the right is a conventional triac-controlled dimmer. VR1 adjusts the dimmed brightness. LDR2 bypasses VR1 to provide maximum brightness when the optical control signal from LD1 illuminates it. LD1 and LDR2 should be tightly coupled and shielded from ambient light.

On the left, we have the "optical inverter": LDR1 detects the ambient light, and turns off LD1 when ambient light is present. In darkness, LD1 is illuminated, and forces the dimmer into full brightness.

^{simulate this circuit – Schematic created using CircuitLab}

Sources for the device models:

• DIAC model

  SUBCKT DB3    1   2
  * TERMINALS:  mt1 mt2
  QN1 5 4 2 NOUT; OFF
  QN2 8 6 7 NOUT; OFF
  QP1 6 8 10 POUT; OFF
  QP2 4 5 9 POUT; OFF
  D1 7 9 DZ
  D2 2 10 DZ
  DF 4 3 DZ; OFF
  DR 6 3 DZ; OFF
  RF 4 3 1.13E+7
  RR 6 3 1.13E+7
  RT2 1 7 0.755
  RH 7 6 10k
  RH2 4 2 10k
  .MODEL DZ D (IS=321F RS=100 N=1.5 IBV=10N BV=30.3)
  .MODEL POUT PNP (IS=321F BF=100 CJE=134p TF=25.5U)
  .MODEL NOUT NPN (IS=321F BF=200 CJE=134p CJC=26.8p TF=1.7U)
  .ENDS
  

• TRIAC model and the page where it came from

  .SUBCKT 2N5568    1    2   3
  * TERMINALS:      mt2  g  mt1
  RF 6 4 40MEG
  RT2 7 1 52.8M
  DR 6 11 DZ; OFF
  DF 4 5 DZ; OFF
  QN1 5 4 3 NOUT
  QP2 4 5 7 POUT
  RS 4 8 52.6
  RGP 8 3 54.5
  RG 8 2 26.4
  RN 9 3 27.8
  DN 9 2 DIN
  DP 2 10 DIP
  RP 3 10 16.2
  GNP 4 5 9 3 51.2M
  GNN 6 7 9 3 38.8M
  GP 7 6 10 3 26.1M
  QN2 11 6 7 NOUT
  QP1 6 11 3 POUT
  RH 6 7 75
  .Model Din D (IS=53.5F)
  .Model Dip D (IS=53.5F N=1.19)
  .Model Dz  D (IS=53.5F N=1.5 IBV=10u BV=400)
  .Model Pout PNP (IS=53.5F BF=5 CJE=235P TF=25.5u)
  .Model Nout NPN (IS=53.5F BF=20 CJE=235P CJC=46.9P TF=1.7u)
  .ENDS