Many combinatorial optimization problems such as the min cost flow problem are equivalent to the ... more Many combinatorial optimization problems such as the min cost flow problem are equivalent to the solution of appropriate DC circuits made up of positive resistors, voltage sources, current sources and ideal diodes. Simulating the DC circuit is an alternative approach to the approximate solution of such problems. However, conventional simulators such as SPICE are too slow for this purpose. This paper describes the structure and performance of a fast DC Analyzer built at EE Department, IIT Bombay specifically for solving large circuits consisting of positive resistors, voltage sources, current sources and diodes. Using the simulator, we have analyzed circuits composed of diodes, positive resistors, current and voltage sources of size upto 700,000 nodes and 1.2 million edges on a 3.0 GHz, 1 GB RAM, PIV processor in at most 1.2 Hrs. We also report a comparative study of the performance of our DC analyzer with that of fastest commercial simulator.
Solution of many combinatorial optimization problems can be found by analyzing appropriate electr... more Solution of many combinatorial optimization problems can be found by analyzing appropriate electrical networks made up of positive resistors, voltage sources, current sources and ideal diodes. This method is an alternative approach for the approximate solution of such problems. Two Graph method based fast simulator is a more suitable option for this purpose than Modified Nodal Analysis based conventional simulators. Using this approach we have made an attempt to solve min cost flow and single source shortest path problems. A planar min cost flow problem of size 200, 000 nodes and 600, 000 edges is solved by our simulator approximately within 0.1% of the optimum solution in about 11 mins. We have exactly solved a planar single source shortest path problem (having negative edge weights also) of size 100, 000 nodes and 600, 000 edges in about 2 mins. We have performed our experiments on a PIV processor having 1 GB RAM.
Partitioning is an important technique for solving graph based problems. The quality of partition... more Partitioning is an important technique for solving graph based problems. The quality of partitions produced by standard methods, for example Fiduccia and Mattheyses (FM) algorithm, depends on the initial random seed partition. In order to get the best partitions, we have to run the partitioner many times with different seed partitions. In this paper, we present a heuristic for producing good seed partitions for partitioning graphs and hypergraphs by analyzing an appropriately derived resistor, current source electrical network and sorting the nodes according to their potentials. This is feasible because we use a special purpose DC analyzer which is very fast and can handle circuits of size up to a million nodes. Experiments have been performed on IBM benchmark hypergraphs on a Pentium-4 machine having 1GB RAM. For larger size hypergraphs, our method outperforms the standard random seed based FM algorithm both in terms of the partitioning time and in terms of the cut-cost.
Physical problems offer scope for macro level parallelization of solution by their essential stru... more Physical problems offer scope for macro level parallelization of solution by their essential structure. For parallelization of electrical network simulation, the most natural structure based method is that of Multiport Decomposition. In this paper this method is used for the simulation of electrical networks consisting of resistances, voltage and current sources using a distributed cluster of weakly coupled processors. At the two levels in which equations are solved in this method we have used sparse LU for both levels in the first scheme and sparse LU in the inner level and Conjugate Gradient in the outer level in the second scheme. Results are presented for planar networks, for the cases where the number of slave processors are 1 and 2, and for circuit sizes upto 8.2 million nodes and 16.4 million edges using 8 slave processors. We use a cluster of Pentium IV processors linked through a 10/100MBPS Ethernet switch.
Many combinatorial optimization problems such as the min cost flow problem are equivalent to the ... more Many combinatorial optimization problems such as the min cost flow problem are equivalent to the solution of appropriate DC circuits made up of positive resistors, voltage sources, current sources and ideal diodes. Simulating the DC circuit is an alternative approach to the approximate solution of such problems. However, conventional simulators such as SPICE are too slow for this purpose. This paper describes the structure and performance of a fast DC Analyzer built at EE Department, IIT Bombay specifically for solving large circuits consisting of positive resistors, voltage sources, current sources and diodes. Using the simulator, we have analyzed circuits composed of diodes, positive resistors, current and voltage sources of size upto 700,000 nodes and 1.2 million edges on a 3.0 GHz, 1 GB RAM, PIV processor in at most 1.2 Hrs. We also report a comparative study of the performance of our DC analyzer with that of fastest commercial simulator.
Solution of many combinatorial optimization problems can be found by analyzing appropriate electr... more Solution of many combinatorial optimization problems can be found by analyzing appropriate electrical networks made up of positive resistors, voltage sources, current sources and ideal diodes. This method is an alternative approach for the approximate solution of such problems. Two Graph method based fast simulator is a more suitable option for this purpose than Modified Nodal Analysis based conventional simulators. Using this approach we have made an attempt to solve min cost flow and single source shortest path problems. A planar min cost flow problem of size 200, 000 nodes and 600, 000 edges is solved by our simulator approximately within 0.1% of the optimum solution in about 11 mins. We have exactly solved a planar single source shortest path problem (having negative edge weights also) of size 100, 000 nodes and 600, 000 edges in about 2 mins. We have performed our experiments on a PIV processor having 1 GB RAM.
Partitioning is an important technique for solving graph based problems. The quality of partition... more Partitioning is an important technique for solving graph based problems. The quality of partitions produced by standard methods, for example Fiduccia and Mattheyses (FM) algorithm, depends on the initial random seed partition. In order to get the best partitions, we have to run the partitioner many times with different seed partitions. In this paper, we present a heuristic for producing good seed partitions for partitioning graphs and hypergraphs by analyzing an appropriately derived resistor, current source electrical network and sorting the nodes according to their potentials. This is feasible because we use a special purpose DC analyzer which is very fast and can handle circuits of size up to a million nodes. Experiments have been performed on IBM benchmark hypergraphs on a Pentium-4 machine having 1GB RAM. For larger size hypergraphs, our method outperforms the standard random seed based FM algorithm both in terms of the partitioning time and in terms of the cut-cost.
Physical problems offer scope for macro level parallelization of solution by their essential stru... more Physical problems offer scope for macro level parallelization of solution by their essential structure. For parallelization of electrical network simulation, the most natural structure based method is that of Multiport Decomposition. In this paper this method is used for the simulation of electrical networks consisting of resistances, voltage and current sources using a distributed cluster of weakly coupled processors. At the two levels in which equations are solved in this method we have used sparse LU for both levels in the first scheme and sparse LU in the inner level and Conjugate Gradient in the outer level in the second scheme. Results are presented for planar networks, for the cases where the number of slave processors are 1 and 2, and for circuit sizes upto 8.2 million nodes and 16.4 million edges using 8 slave processors. We use a cluster of Pentium IV processors linked through a 10/100MBPS Ethernet switch.
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Papers by Gaurav Trivedi