This paper describes the development of glucose biosensors based on carbon nanotube (CNT) nanoele... more This paper describes the development of glucose biosensors based on carbon nanotube (CNT) nanoelectrode ensembles (NEEs) for the selective detection of glucose. Glucose oxidase was covalently immobilized on CNT NEEs via carbodiimide chemistry by forming amide linkages between their amine residues and carboxylic acid groups on the CNT tips. The catalytic reduction of hydrogen peroxide liberated from the enzymatic reaction of glucose oxidase upon the glucose and oxygen on CNT NEEs leads to the selective detection of glucose. The biosensor effectively performs a selective electrochemical analysis of glucose in the presence of common interferents (e.g., acetaminophen, uric and ascorbic acids), avoiding the generation of an overlapping signal from such interferers. Such an operation eliminates the need for permselective membrane barriers or artificial electron mediators, thus greatly simplifying the sensor design and fabrication.
Abstruct-Using a combination of architecture optimization techniques and unconventional circuit d... more Abstruct-Using a combination of architecture optimization techniques and unconventional circuit designs, a 60-MHz decision-feedback equalizer (DFE) chip is presented for high-bitrate digital modem applications. The equalizer can accommodate a wide variety of modulation formats (quaternary phase-shift keying (QPSK), 16, 64, 256 quadrature amplitude modulation (QAM)) and achieves a peak throughput rate of 480 Mb/s. The chip contains four complex-valued programmable filter taps, and also incorporates coefficient updating circuitry for implementing the LMS adaptive algorithm with user-selectable adaptation step sizes. Cut-set retiming architecture techniques were used so that the chips could be cascaded to implement longer equalizer lengths without any speed degradation, and a circuit design technique called adaptively biased pseudo-NMOS logic (APNL) was adopted to reduce on-chip critical-path delays. The transistor count is 70 000 within a 4.9-mm x 7.0-mm die area in 1.2-pm CMOS. The fully parallel chip architecture achieves a computational throughput of 1.44 billion operations per second (GOPS).
A mixed-signal digital cable-TV transceiver IC containing two distinctly separate quadrature ampl... more A mixed-signal digital cable-TV transceiver IC containing two distinctly separate quadrature amplitude modulation (QAM) receivers and a single QAM modulator has been designed. An integrated 10-b analog-to-digital converter (A/D) interfaces the first receiver directly to an analog signal. This receiver demodulates 4/16/32/64/128/256-QAM signals carrying the television programs or cable modem data with a variable symbol rate from 1 to 7 MBaud. A 6-b A/D is integrated to interface the second receiver to an analog signal. This receiver, used by cable operators for access control, demodulates quadrature phase shift keying (QPSK) signals with a variable symbol rate from 0.75 to 1.6 MBaud. The upstream modulator provides two-way communication required for interactive television or cable modem services. Capable of QPSK/16-QAM modulation with a variable transmission rate up to 25 Mb/s, the modulator also includes an integrated 10-b digital-to-analog converter to provide radio-frequency analog output from 0 to 65 MHz. Both receivers and the transmitter incorporate on-chip forward error correction compliant with multiple worldwide standards allowing global deployment. The carrier, phase, and timing recovery for each receiver is achieved with on-chip tracking loops. Adaptive decision feedback equalizers are incorporated to eliminate intersymbol interference. The transmitter incorporates preamble prepending and preequalization to facilitate reception. The device further integrates access control message separation, set-top box control circuitry, and a parallel microprocessor bus interface to boost system performance. The design employs a combination of semicustom and custom circuit design techniques for speed, mixed-signal performance, and layout density. Fabricated in a single poly, four-layer-metal, 0.35-m standard CMOS process, the chip area is 64 mm 2 . The device is packaged in a 256 tape ball grid array (TBGA), and dissipates 3 W at 3.3 V.
A bit-level pipelined 12 x 12-b two's-complement multiplier with a 27-b accumulator has been desi... more A bit-level pipelined 12 x 12-b two's-complement multiplier with a 27-b accumulator has been designed and fabricated in a 1.0-pm p-well CMOS technology. A new "quasi N-P domino logic" structure has been adopted to increase the throughput rate, and special pipeline structures were used in the accumulator to reduce the total latency. The chip complexity is approximately 10 OOO transistors and the die area is 2.5
To accomplish timing recoverylsynthesis in highspeed communication systems, a 24-b numerically co... more To accomplish timing recoverylsynthesis in highspeed communication systems, a 24-b numerically controlled oscillator (NCO) IC using a circuit design technique called true single-phase clock (TSPC) pipelined CMOS has been fabricated in a standard 1.2-pm CMOS process. The device achieves a maximum tested input clock rate of 700 MHz, which results in an output frequency tuning range from dc up to 350 MHz with a 41.7-Hz tuning resolution and a peak-to-peak phase jitter of 1.4 ns. The 1.7 x 1.7-mm2 IC dissipates 850 mW with a single 5-V supply, which is substantially lower than similar ECL and GaAs devices.
A 70 Mb/s variable-rate 1024-quadrature amplitude modulated (QAM) cable receiver IC with integrat... more A 70 Mb/s variable-rate 1024-quadrature amplitude modulated (QAM) cable receiver IC with integrated 10 b analogto-digital converter (ADC) and forward error correction (FEC) decoder is presented. The chip accepts an analog 2 V pp V pp V pp differential QAM signal centered at an intermediate frequency. The integrated 10 b ADC digitizes the IF signal, and all subsequent signal processing, including demodulation, timing/carrier recovery, adaptive equalization, and FEC, is performed digitally. The receiver IC is capable of receiving 4, 16, 32, 64, 128, 256, and 1024-QAM modulation formats. The 0.5-m triple level metal N-well CMOS chip has a complexity of 650 k transistors with a core area of 4.9 2 4.9 mm 2 : Power dissipation is 1.8 W at 7 MBaud and 5 V.
This paper describes the development of glucose biosensors based on carbon nanotube (CNT) nanoele... more This paper describes the development of glucose biosensors based on carbon nanotube (CNT) nanoelectrode ensembles (NEEs) for the selective detection of glucose. Glucose oxidase was covalently immobilized on CNT NEEs via carbodiimide chemistry by forming amide linkages between their amine residues and carboxylic acid groups on the CNT tips. The catalytic reduction of hydrogen peroxide liberated from the enzymatic reaction of glucose oxidase upon the glucose and oxygen on CNT NEEs leads to the selective detection of glucose. The biosensor effectively performs a selective electrochemical analysis of glucose in the presence of common interferents (e.g., acetaminophen, uric and ascorbic acids), avoiding the generation of an overlapping signal from such interferers. Such an operation eliminates the need for permselective membrane barriers or artificial electron mediators, thus greatly simplifying the sensor design and fabrication.
Abstruct-Using a combination of architecture optimization techniques and unconventional circuit d... more Abstruct-Using a combination of architecture optimization techniques and unconventional circuit designs, a 60-MHz decision-feedback equalizer (DFE) chip is presented for high-bitrate digital modem applications. The equalizer can accommodate a wide variety of modulation formats (quaternary phase-shift keying (QPSK), 16, 64, 256 quadrature amplitude modulation (QAM)) and achieves a peak throughput rate of 480 Mb/s. The chip contains four complex-valued programmable filter taps, and also incorporates coefficient updating circuitry for implementing the LMS adaptive algorithm with user-selectable adaptation step sizes. Cut-set retiming architecture techniques were used so that the chips could be cascaded to implement longer equalizer lengths without any speed degradation, and a circuit design technique called adaptively biased pseudo-NMOS logic (APNL) was adopted to reduce on-chip critical-path delays. The transistor count is 70 000 within a 4.9-mm x 7.0-mm die area in 1.2-pm CMOS. The fully parallel chip architecture achieves a computational throughput of 1.44 billion operations per second (GOPS).
A mixed-signal digital cable-TV transceiver IC containing two distinctly separate quadrature ampl... more A mixed-signal digital cable-TV transceiver IC containing two distinctly separate quadrature amplitude modulation (QAM) receivers and a single QAM modulator has been designed. An integrated 10-b analog-to-digital converter (A/D) interfaces the first receiver directly to an analog signal. This receiver demodulates 4/16/32/64/128/256-QAM signals carrying the television programs or cable modem data with a variable symbol rate from 1 to 7 MBaud. A 6-b A/D is integrated to interface the second receiver to an analog signal. This receiver, used by cable operators for access control, demodulates quadrature phase shift keying (QPSK) signals with a variable symbol rate from 0.75 to 1.6 MBaud. The upstream modulator provides two-way communication required for interactive television or cable modem services. Capable of QPSK/16-QAM modulation with a variable transmission rate up to 25 Mb/s, the modulator also includes an integrated 10-b digital-to-analog converter to provide radio-frequency analog output from 0 to 65 MHz. Both receivers and the transmitter incorporate on-chip forward error correction compliant with multiple worldwide standards allowing global deployment. The carrier, phase, and timing recovery for each receiver is achieved with on-chip tracking loops. Adaptive decision feedback equalizers are incorporated to eliminate intersymbol interference. The transmitter incorporates preamble prepending and preequalization to facilitate reception. The device further integrates access control message separation, set-top box control circuitry, and a parallel microprocessor bus interface to boost system performance. The design employs a combination of semicustom and custom circuit design techniques for speed, mixed-signal performance, and layout density. Fabricated in a single poly, four-layer-metal, 0.35-m standard CMOS process, the chip area is 64 mm 2 . The device is packaged in a 256 tape ball grid array (TBGA), and dissipates 3 W at 3.3 V.
A bit-level pipelined 12 x 12-b two's-complement multiplier with a 27-b accumulator has been desi... more A bit-level pipelined 12 x 12-b two's-complement multiplier with a 27-b accumulator has been designed and fabricated in a 1.0-pm p-well CMOS technology. A new "quasi N-P domino logic" structure has been adopted to increase the throughput rate, and special pipeline structures were used in the accumulator to reduce the total latency. The chip complexity is approximately 10 OOO transistors and the die area is 2.5
To accomplish timing recoverylsynthesis in highspeed communication systems, a 24-b numerically co... more To accomplish timing recoverylsynthesis in highspeed communication systems, a 24-b numerically controlled oscillator (NCO) IC using a circuit design technique called true single-phase clock (TSPC) pipelined CMOS has been fabricated in a standard 1.2-pm CMOS process. The device achieves a maximum tested input clock rate of 700 MHz, which results in an output frequency tuning range from dc up to 350 MHz with a 41.7-Hz tuning resolution and a peak-to-peak phase jitter of 1.4 ns. The 1.7 x 1.7-mm2 IC dissipates 850 mW with a single 5-V supply, which is substantially lower than similar ECL and GaAs devices.
A 70 Mb/s variable-rate 1024-quadrature amplitude modulated (QAM) cable receiver IC with integrat... more A 70 Mb/s variable-rate 1024-quadrature amplitude modulated (QAM) cable receiver IC with integrated 10 b analogto-digital converter (ADC) and forward error correction (FEC) decoder is presented. The chip accepts an analog 2 V pp V pp V pp differential QAM signal centered at an intermediate frequency. The integrated 10 b ADC digitizes the IF signal, and all subsequent signal processing, including demodulation, timing/carrier recovery, adaptive equalization, and FEC, is performed digitally. The receiver IC is capable of receiving 4, 16, 32, 64, 128, 256, and 1024-QAM modulation formats. The 0.5-m triple level metal N-well CMOS chip has a complexity of 650 k transistors with a core area of 4.9 2 4.9 mm 2 : Power dissipation is 1.8 W at 7 MBaud and 5 V.
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